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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. 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user?s manual pd789071 pd789071(a) pd789072 pd789072(a) pd789074 pd789074(a) pd78f9076 pd789074 subseries 8-bit single-chip microcontrollers printed in japan document no. u14801ej3v1ud00 (3rd edition) date published october 2005 n cp(k) ?
user?s manual u14801ej3v1ud 2 [memo]
user?s manual u14801ej3v1ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
user?s manual u14801ej3v1ud 4 eeprom and fip are trademarks of nec electronics corporation. windows and windows nt are either re gistered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trad emarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of august, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, cus tomers must incorporate sufficient safety m easures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
user?s manual u14801ej3v1ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j05.6 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-265 40 10 ? tyskland filial taeby, sweden tel: 08-63 87 200 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
user?s manual u14801ej3v1ud 6 major revisions in this edition page description u14801ej2v0ud00 u14801ej3v0ud00 throughout ? addition of pd789071(a), 789072(a), and 789074(a) ? addition of description of expanded-specificat ion products pp.20, 22, 29 chapter 1 general ? addition of 1.1 expanded-specification products and conventional products ? addition of 1.5 quality grades ? addition of 1.10 differences between standard quality grade products and (a) products pp.89, 90, 91, 95 chapter 6 16-bit timer 90 ? modification of description of 6.4.1 operation as timer interrupt ? modification of figure 6-6. timing of timer interrupt operation ? modification of description of 6.4.2 operation as timer output ? modification of figure 6-8. timer output timing ? addition of 6.5 notes on using 16-bit timer 90 p.108 chapter 7 8-bit timer/event counter 80 ? addition of 7.5 (3) timer operation after compare re gister is rewritten during pwm output ? addition of 7.5 (4) cautions when stop mode is set ? addition of 7.5 (5) start timing of external event counter p.174 chapter 13 pd78f9076 ? total revision of description of flash memory programming p.195 addition of chapter 15 electrical specificatio ns (expanded-specification products) p.211 chapter 16 electrical specificat ions (conventional products) ? modification of table of recommended oscillator constant p.223 chapter 18 recommended soldering conditions ? change of recommended soldering conditions of pd78f9076 p.229 appendix a development tools ? modification of description of a.5 debugging tools (hardware) p.231 addition of appendix b notes on target system design u14801ej3v0ud00 u14801ej3v1ud00 p.21 modification of 1.4 ordering information p.22 modification of 1.5 quality grades p.224 addition of table 18-1. surface mounting type soldering conditions (2/2) the mark shows major revised points.
user?s manual u14801ej3v1ud 7 introduction readers this manual is intended for user engineer s who wish to gain an understanding of the functions of the pd789074 subseries in order to design and develop its application systems and programs. purpose this manual is intended to give users an understanding of the f unctions described in the organization below. organization two manuals are available for the pd789074 subseries: this manual and the instruction manual (common to the 78k/0s series). pd789074 subseries user's manual 78k/0s series user's manual instructions ? pin functions ? internal block functions ? interrupts ? other internal peripheral functions ? electrical specifications ? cpu function ? instruction set ? instruction description how to read this manual it is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. for users who use this doc ument as the manual for the pd789071(a), 789072(a), or 789074(a) the only differences between standar d products and (a) products are the quality grades and electrical specifications (refer to 1.10 differences between standard quality grade products and (a) products ). for the (a) products, read the part numbers as follows. pd789071 pd789071(a) pd789072 pd789072(a) pd789074 pd789074(a) to understand the overa ll functions of the pd789074 subseries read this manual in the order of the contents . how to read register formats the name of a bit whose number is enclosed with <> is reserved in the assembler and is defined in the c compiler by the header file sfrbit.h. to learn the detailed functions of a register whose register name is known see appendix c register index . to learn details of the instruct ion functions of the 78k/0s series refer to 78k/0s series instructions user's manual (u11047e) available separately. to learn the electrical specifications of the pd789074 subseries refer to chapter 15 electrical specifications (expanded- specification products) and chapter 16 electrical specifications (conventional products) . caution the application examples in th is manual are created for "standard" quality grade products for general electric equipment. when using the application examples in this manual for purposes which require "special" quality grades, thoroughl y examine the quality grade of each part and circuit actually used.
user?s manual u14801ej3v1ud 8 conversions data significance: higher digits on the left and lower digits on the right active low representation: (overscore over pin or signal name) note : footnote for item marked note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd789074 subseries user?s manual this manual 78k/0s series instructions user?s manual u11047e documents related to development tools (software) (user?s manuals) document name document no operation u14876e language u14877e ra78k0s assembler package structured assembly language u11623e operation u14871e cc78k0s c compiler language u14872e operation (windows tm based) u15373e sm78k series system simulator ver. 2.30 or later external parts user open interface specifications u15802e id78k series integrated debugger ver. 2.30 or later operation (windows based) u15185e project manager ver. 3.12 or later (windows based) u14610e documents related to development tools (hardware) (user?s manuals) document name document no. ie-78k0s-ns in-circuit emulator u13549e ie-78k0s-ns-a in-circuit emulator u15207e ie-789046-ns-em1 emulation board u14433e caution the related docum ents listed above are subject to change wit hout notice. be sure to use the latest version of each document for designing.
user?s manual u14801ej3v1ud 9 documents for flash memory writing document name document no. pg-fp3 flash memory progr ammer user?s manual u13502e pg-fp4 flash memory progr ammer user?s manual u15260e other related documents document name document no. semiconductor selection guide - products and packages - x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device mount manual? webs ite (http://www.necel.com/pkg/en/mount/index.html) caution the related docum ents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
user?s manual u14801ej3v1ud 10 contents chapter 1 general........................................................................................................... ................20 1.1 expanded-specification products and conventi onal products ...........................................20 1.2 features ................................................................................................................. .....................21 1.3 applications............................................................................................................. ...................21 1.4 ordering information ..................................................................................................... ............21 1.5 quality grades........................................................................................................... .................22 1.6 pin configuration (top vi ew)............................................................................................. .......23 1. 7 78k/0s series lineup....................................................................................................... ..........24 1.8 block diagram ............................................................................................................ ................27 1.9 overview of functions.................................................................................................... ...........28 1.10 differences between standard quality grade products and (a) products .........................29 chapter 2 pin functio ns .................................................................................................... ...........30 2.1 pin function list ........................................................................................................ ................30 2.2 description of pin functions ............................................................................................. .......32 2.2.1 p00 to p07 (p ort 0).................................................................................................... .................. 32 2.2.2 p10 to p15 (p ort 1).................................................................................................... .................. 32 2.2.3 p20 to p27 (p ort 2).................................................................................................... .................. 32 2.2.4 p30, p31 (por t 3)...................................................................................................... ................... 33 2.2.5 reset .................................................................................................................. ...................... 33 2.2.6 x1, x2................................................................................................................. ......................... 33 2.2.7 v dd ............................................................................................................................... ............... 33 2.2.8 v ss ............................................................................................................................... ................ 33 2.2.9 v pp ( pd78f9076 onl y)............................................................................................................... 3 4 2.2.10 ic (mask rom versi on onl y) ............................................................................................ ........... 34 2.3 pin i/o circuits and recommended connection of unused pins.........................................35 chapter 3 cpu archi tecture ................................................................................................. .....37 3.1 memory space............................................................................................................. ...............37 3.1.1 internal pr ogram memory space.......................................................................................... ........ 41 3.1.2 internal data memory (internal high-s peed ram) s pace ............................................................. 41 3.1.3 special functi on register (sfr) area................................................................................... ......... 41 3.1.4 data me mory addr essing ................................................................................................. ........... 42 3.2 processor registers ...................................................................................................... ............46 3.2.1 contro l regist ers ...................................................................................................... .................... 46 3.2.2 general- purpose regi sters.............................................................................................. ............. 49 3.2.3 special func tion register s (sfrs) ...................................................................................... .......... 50 3.3 instruction address addressing .................................. ......................................................... ...53 3.3.1 relati ve addre ssing .................................................................................................... ................. 53 3.3.2 immedi ate addre ssing ................................................................................................... .............. 54
user?s manual u14801ej3v1ud 11 3.3.3 table i ndirect addr essing.............................................................................................. ............... 55 3.3.4 regist er addre ssing.................................................................................................... ................. 55 3.4 operand address addressing ................................... ............................................................ ...56 3.4.1 direc t addre ssing ...................................................................................................... ................... 56 3.4.2 short di rect addr essing................................................................................................ ................ 57 3.4.3 special function register (sfr ) addre ssing ............................................................................. .... 58 3.4.4 regist er addre ssing.................................................................................................... ................. 59 3.4.5 register indirect addressi ng ........................................................................................... ............. 60 3.4.6 bas ed addre ssing ....................................................................................................... ................. 61 3.4.7 sta ck addre ssing ....................................................................................................... .................. 61 chapter 4 port functions ......................................... .......................................................... ........62 4.1 port functions ........................................................................................................... .................62 4.2 port configuration ....................................................................................................... ..............64 4.2.1 port 0................................................................................................................. .......................... 64 4.2.2 port 1................................................................................................................. .......................... 65 4.2.3 port 2................................................................................................................. .......................... 66 4.2.4 port 3................................................................................................................. .......................... 70 4.3 port function control register s .......................................................................................... ....71 4.4 operation of port functions ................................... ........................................................... .......74 4.4.1 writi ng to i/o port .................................................................................................... .................... 74 4.4.2 reading from i/o port .................................................................................................. ................ 74 4.4.3 arithmetic operation of i/o port....................................................................................... ............. 74 chapter 5 clock generator ..................................... ............................................................. ....75 5.1 clock generator functions ...................................... .......................................................... .......75 5.2 clock generator configuration ............................... ............................................................. ....75 5.3 clock generator control register........................... .............................................................. ...76 5.4 system clock oscillators ................................................................................................. .........77 5.4.1 system clock osc illator ................................................................................................ ................ 77 5.4.2 examples of inco rrect resonator connec tion............................................................................. ... 78 5.4.3 fr equency di vider ...................................................................................................... .................. 79 5.5 clock generator operation ..................................... ........................................................... .......80 5.6 changing setting of cpu clock............................................................................................ ....81 5.6.1 time required fo r switching cpu cl ock .................................................................................. ...... 81 5.6.2 switch ing cpu clock .................................................................................................... ............... 81 chapter 6 16-bit timer 90 ................................................................................................. .............82 6.1 functions of 16-bit timer 90................................... .......................................................... ........82 6.2 configuration of 16-bit timer 90 ............................ ............................................................. .....82 6.3 control registers of 16-bit timer 90...................... ............................................................... ...85 6.4 operation of 16-bit timer 90 ................................ ............................................................. ........89 6.4.1 operation as timer interr upt ........................................................................................... .............. 89 6.4.2 operati on as time r out put .............................................................................................. .............. 91
user?s manual u14801ej3v1ud 12 6.4.3 capt ure operat ion...................................................................................................... .................. 92 6.4.4 16-bit time r counter 90 r eadou t........................................................................................ ............ 93 6.4.5 buzzer output oper ation ................................................................................................ .............. 94 6.5 notes on using 16-bit timer 90................................ ........................................................... .....95 6.5.1 restrictions on rewrit ing16-bit compare register 90.................................................................... . 95 chapter 7 8-bit timer/event counter 80................... ............................................................97 7.1 functions of 8-bit timer/event counter 80............. ................................................................97 7.2 configuration of 8-bit timer/event counter 80 ... ...................................................................98 7.3 8-bit timer/event counter 80 control registers .... ................................................................99 7.4 operation of 8-bit timer/event counter 80 .......... .................................................................101 7.4.1 operation as interval timer ............................................................................................ ............ 101 7.4.2 operation as external ev ent c ounter .................................................................................... ...... 103 7.4.3 operation as square-wa ve out put........................................................................................ ...... 104 7.4.4 operati on as pw m out put ................................................................................................ ......... 106 7.5 notes on using 8-bit timer/event counter 80 ........ ..............................................................107 chapter 8 watchdog timer ................................................................................................... ....109 8.1 watchdog timer functions................................................................................................. ....109 8.2 watchdog timer configuration ............................................................................................. .110 8.3 watchdog timer control regist ers........................................................................................1 11 8.4 watchdog timer operation................................................................................................. ....113 8.4.1 operation as watchdog timer............................................................................................ ......... 113 8.4.2 operation as interval timer ............................................................................................ ............ 114 chapter 9 serial interface 20 ............................................................................................. ...115 9.1 functions of serial interface 20............................. ............................................................ .....115 9.2 configuration of serial interface 20 ..................................................................................... ..115 9.3 control registers of serial interface 20 ................................................................................1 19 9.4 operation of serial interface 20..................... .................................................................... .....126 9.4.1 operat ion stop mode .................................................................................................... ............. 126 9.4.2 asynchronous serial interface (u art) m ode............................................................................. 1 27 9.4.3 3-wire serial i/o mode ................................................................................................. .............. 140 chapter 10 interrupt functions .................................... ........................................................1 50 10.1 interrupt function types................................................................................................ .........150 10.2 interrupt sources and confi guration ..................................................................................... 150 10.3 interrupt function control re gisters.................................................................................... .153 10.4 interrupt processing operation............................. ............................................................. ....158 10.4.1 non-maskable interrupt request acknowledgm ent operat ion ..................................................... 158 10.4.2 maskable interrupt r equest acknowledgment operati on............................................................. 160 10.4.3 multiple in terrupt se rvicing.......................................................................................... ............... 162 10.4.4 interr upt reques t hold ................................................................................................ ................ 164
user?s manual u14801ej3v1ud 13 chapter 11 standby function ..................................... ........................................................... ..165 11.1 standby function and configurat ion.....................................................................................1 65 11.1.1 standby func tion...................................................................................................... .................. 165 11.1.2 standby functi on control regist er ..................................................................................... .......... 166 11.2 operation of standby function ............................... ............................................................ ...167 11.2.1 ha lt m ode ............................................................................................................. .................. 167 11.2.2 st op m ode............................................................................................................. .................. 169 chapter 12 reset function .................................................................................................. .....171 chapter 13 pd78f9076...................................................................................................................174 13.1 flash memory characteristics ................................ ............................................................ ....175 13.1.1 progra mming envir onment ............................................................................................... ......... 175 13.1.2 comm unication mode................................................................................................... ............. 176 13.1.3 on-boar d pin c onnecti ons.............................................................................................. ............ 179 13.1.4 connection of adapt er for flas h writ ing ............................................................................... ....... 182 chapter 14 instruction set overview .................... .............................................................185 14.1 operation ............................................................................................................... ...................185 14.1.1 operand identifie rs and descrip tion me thods ........................................................................... . 185 14.1.2 description of "operation" column ..................................................................................... ........ 186 14.1.3 description of "flag" column.......................................................................................... ............ 186 14.2 operation list .......................................................................................................... .................187 14.3 instructions listed by addressing type ............... ................................................................192 chapter 15 electrical specifications (expanded-specification products)......195 chapter 16 electrical specifications (con ventional products) ..........................209 chapter 17 package drawing ..................................... ............................................................ .222 chapter 18 recommended soldering conditions.. .........................................................223 appendix a development tools............................................................................................... 225 a.1 software package ......................................................................................................... ...........227 a.2 language processing software ................................... .......................................................... 227 a.3 control software .......................................................................................................... ............228 a.4 flash memory writing tools ............................................................................................... ....229 a.5 debugging tools (hardware) ..................................... .......................................................... ...229 a.6 debugging tools (software) ...................................... ......................................................... ....230 appendix b notes on target system design ... ................................................................231
user?s manual u14801ej3v1ud 14 appendix c register index .................................................................................................. .......233 c.1 register name index (alphabetic order)................. ..............................................................233 c.2 register symbol index (alphabetic order) .......... .................................................................235 appendix d revision history ................................................................................................ .....237
user?s manual u14801ej3v1ud 15 list of figures (1/3) figure no. title page 2-1 pin i/o circuit s .......................................................................................................... ........................................36 3-1 memory map ( pd789071) ...................................................................................................................... .........37 3-2 memory map ( pd789072) ...................................................................................................................... .........38 3-3 memory map ( pd789074) ...................................................................................................................... .........39 3-4 memory map ( pd78f 9076) ..................................................................................................................... .......40 3-5 data memory addressing ( pd789071) ...........................................................................................................42 3-6 data memory addressing ( pd789072) ...........................................................................................................43 3-7 data memory addressing ( pd789074) ...........................................................................................................44 3-8 data memory addressing ( pd78f9076) .........................................................................................................45 3-9 program counter configur ation ............................................................................................. ...........................46 3-10 program status word confi guratio n ........................................................................................ .........................46 3-11 stack pointe r configur ation .............................................................................................. ................................48 3-12 data to be sa ved to sta ck memory ......................................................................................... .........................48 3-13 data to be rest ored from st ack me mory .................................................................................... .....................48 3-14 general-purpose regi ster confi guratio n ................................................................................... .......................49 4-1 port types ................................................................................................................ ........................................62 4-2 block diagram of p00 to p07 ............................................................................................... .............................64 4-3 block diagram of p10 to p15 ............................................................................................... .............................65 4-4 block diagr am of p20 ...................................................................................................... .................................66 4-5 block diagr am of p21 ...................................................................................................... .................................67 4-6 block diagram of p22 to p26 ............................................................................................... .............................68 4-7 block diagr am of p27 ...................................................................................................... .................................69 4-8 block diagram of p30 and p3 1 .............................................................................................. ...........................70 4-9 format of po rt mode r egister.............................................................................................. .............................71 4-10 format of pull-up resi stor option r egister 0............................................................................. .......................72 4-11 format of pull-up resi stor option r egister b2 ............................................................................ .....................73 5-1 block diagram of clock g enerat or.......................................................................................... ..........................75 5-2 format of processo r clock contro l regi ster................................................................................ .....................76 5-3 external circuit of system clock oscilla tor ............................................................................... ........................77 5-4 examples of incorre ct resonator connec tion................................................................................ ...................78 5-5 switching between s ystem clock and cpu clo ck .............................................................................. .............81 6-1 block diagram of 16-bit timer 90 .......................................................................................... ...........................83 6-2 format of 16-bit timer mode control r egister 90 ........................................................................... .................86 6-3 format of buzzer out put control r egister 90 ............................................................................... ....................87 6-4 format of port mode regi ster 3............................................................................................ ............................88
user?s manual u14801ej3v1ud 16 list of figures (2/3) figure no. title page 6-5 settings of 16-bit timer mode control r egister 90 for timer in terrupt o peration........................................... ..89 6-6 timing of timer interrupt o peratio n ....................................................................................... ...........................90 6-7 settings of 16-bit timer mode control register 90 for timer output o peratio n .............................................. .91 6-8 timer ou tput ti ming ....................................................................................................... ..................................91 6-9 settings of 16-bit timer mode contro l register 90 for c apture oper ation ................................................... ....92 6-10 capture operation ti ming (with both edges of cpt90 pin specif ied)........................................................ ......92 6-11 16-bit timer count er 90 readout timing ................................................................................... ......................93 6-12 settings of buzzer output control r egister 90 for buzzer output o peration................................................ ....94 7-1 block diagram of 8-bi t timer/event counter 80 ............................................................................. ..................98 7-2 format of 8-bit timer mode control r egister 80 ............................................................................ ..................99 7-3 format of port mode regi ster 2............................................................................................ ..........................100 7-4 interval time r operati on timi ng ........................................................................................... ..........................102 7-5 external event counter operati on timing (with risi ng edge spec ifi ed) ...................................................... ...103 7-6 square-wave output timing ................................................................................................. .........................105 7-7 pwm out put ti ming ......................................................................................................... ..............................106 7-8 start timing of 8- bit timer c ounter 80 .................................................................................... .......................107 7-9 external event c ounter operat ion ti ming ................................................................................... ...................107 7-10 operation timing after compare regi ster is rewritten during pwm output .................................................10 8 8-1 block diagram of watchdog timer ........................................................................................... ......................110 8-2 format of watchdog time r clock selecti on regi ster ......................................................................... ............111 8-3 format of watchdog timer mode regist er .................................................................................... .................112 9-1 block diagram of serial inte rface 20....................................................................................... ........................116 9-2 block diagram of b aud rate gener ator 20.................................................................................... .................117 9-3 format of serial o peration mode r egister 20 ............................................................................... .................119 9-4 format of asynchronous seri al interface m ode regist er 20.................................................................. .........120 9-5 format of asynchronous serial interface status regist er 20 ................................................................ .........122 9-6 format of baud rate gener ator control register 20......................................................................... .............123 9-7 format of asynchronous serial interface transmi t/receive data............................................................. ......133 9-8 asynchronous serial interface tr ansmission completion interrupt timing .................................................... .135 9-9 asynchronous serial interface re ception completion interrupt timing ....................................................... ...136 9-10 receive error ti ming ..................................................................................................... .................................137 9-11 3-wire seri al i/o mode timing ........................................................................................... ............................143 10-1 basic configuration of interrupt func tion................................................................................ ........................152 10-2 format of interrupt request flag regist er................................................................................ ......................154 10-3 format of interr upt mask flag regist er ................................................................................... .......................155
user?s manual u14801ej3v1ud 17 list of figures (3/3) figure no. title page 10-4 format of external in terrupt mode r egister 0 ............................................................................. ....................156 10-5 program status word confi guratio n ........................................................................................ .......................157 10-6 flowchart from non-maskable interr upt request generation to ackno wledgment .........................................159 10-7 timing of non-maskable in terrupt request acknowl edgment .................................................................. ......159 10-8 acknowledgment of non -maskable interr upt r equest ......................................................................... ...........159 10-9 interrupt request ackno wledgment proce ssing algor ithm .................................................................... .........161 10-10 interrupt request acknowledgment timing (example of mov a,r) ............................................................ ....162 10-11 interrupt request acknowledgment timing (when interrupt request flag is set at last clock during instruct ion exec ution) ................................................................................................. .........................162 10-12 example of mu ltiple in terrupts.......................................................................................... ...............................163 11-1 format of oscillation stabiliz ation time sele ction r egist er .............................................................. ..............166 11-2 releasing halt mode by interr upt......................................................................................... ........................167 11-3 releasing halt mode by r eset i nput ....................................................................................... ..................168 11-4 releasing stop mode by interr upt ......................................................................................... .......................170 11-5 releasing stop mode by r eset i nput....................................................................................... ..................170 12-1 block diagram of reset function.......................................................................................... ..........................171 12-2 reset timing by reset input .............................................................................................. ..........................172 12-3 reset timing by watchdog timer overflow.................................................................................. ..................172 12-4 reset timing by reset input in stop mode................................................................................. ...............172 13-1 environment for writing program to fl ash me mory ........................................................................... .............175 13-2 communication mode selection format ....................................................................................... ..................176 13-3 example of connection with dedicated flas h progra mmer ..................................................................... .......177 13-4 v pp pin connecti on exam ple ........................................................................................................ ..................179 13-5 signal conflict (seria l interface input pin).............................................................................. .........................180 13-6 malfunction of another device ............................................................................................. ...........................180 13-7 signal conflic t (reset pin)............................................................................................... .............................181 13-8 wiring example for flash writing adapter using 3-wi re seri al i/o.......................................................... .......182 13-9 wiring example for flash writing adapter using uart ....................................................................... ..........183 13-10 wiring example for flash writ ing adapter usi ng pseudo 3- wire............................................................. .......184 a-1 developm ent t ools .......................................................................................................... ...............................226 b-1 distance between in-circuit emulator and conv ersion a dapter ................................................................ .....231 b-2 connection condition of target system ...................................................................................... ...................232
user?s manual u14801ej3v1ud 18 list of tables (1/2) table no. title page 1-1 differences between expanded-specificat ion products and conv entional pr oducts ........................................20 1-2 differences between standard qua lity grade products and (a) pr oducts ....................................................... 29 2-1 types of pin i/o circuits and recommended connection of unus ed pi ns ....................................................... 35 3-1 internal rom capac ity..................................................................................................... .................................41 3-2 vector table .............................................................................................................. .......................................41 3-3 special func tion regi sters ................................................................................................ ...............................51 4-1 port functi ons............................................................................................................ .......................................63 4-2 configurat ion of port ..................................................................................................... ....................................64 4-3 port mode register and output latch settings for using alternate functi ons................................................ ..72 5-1 configuration of clock g enerat or.......................................................................................... ............................75 5-2 maximum time requir ed for switchi ng cpu clock ............................................................................. .............81 6-1 configuration of 16-bit timer 90 .......................................................................................... .............................82 6-2 interval time of 16-bit timer 90.......................................................................................... ..............................89 6-3 settings of captur e edge.................................................................................................. ................................92 6-4 buzzer frequency of 16-bit ti mer 90 ....................................................................................... ........................94 7-1 interval time of 8- bit timer/event counter 80............................................................................. .....................97 7-2 square-wave output range of 8-bit timer/ev ent count er 80 .................................................................. .......97 7-3 configuration of 8-bi t timer/event counter 80 ............................................................................. ....................98 7-4 interval time of 8- bit timer/event counter 80............................................................................. ...................101 7-5 square-wave output range of 8-bit timer/ event c ounter ..................................................................... .......104 8-1 inadvertent loop detecti on time of wa tchdog ti mer......................................................................... ............109 8-2 interv al time ............................................................................................................. ......................................109 8-3 configuration of watchdog timer ........................................................................................... ........................110 8-4 inadvertent loop detecti on time of wa tchdog ti mer......................................................................... ............113 8-5 interval generated using interv al timer ................................................................................... ......................114 9-1 configuration of serial inte rface 20...................................................................................... ...........................115 9-2 operating mode settings of serial in terfac e 20 ............................................................................ ..................121 9-3 example of relationship between system clo ck and baud rate................................................................ ...124 9-4 relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) ...........125 9-5 example of relationship between system clo ck and baud rate................................................................ ...132 9-6 relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) ...........132
user?s manual u14801ej3v1ud 19 list of tables (2/2) table no. title page 9-7 receive error c auses ...................................................................................................... ...............................137 10-1 interrupt sour ces ........................................................................................................ ....................................151 10-2 interrupt request si gnals and corres ponding fl ags........................................................................ ...............153 10-3 time from generation of mask able interrupt reques t to serv icing.......................................................... .......160 11-1 operation status es in ha lt mode .......................................................................................... .......................167 11-2 operation after releasing ha lt mode...................................................................................... .....................168 11-3 operation status es in st op mode.......................................................................................... .......................169 11-4 operation after releasing st op mode ...................................................................................... ....................170 12-1 status of hard ware afte r reset ........................................................................................... ...........................173 13-1 differences between flash memory and mask rom vers ions ................................................................... ....174 13-2 communica tion mode list.................................................................................................. .............................176 13-3 pin c onnection list ...................................................................................................... ...................................178 14-1 operand identifiers and descripti on met hods .............................................................................. ...................185 18-1 surface mounting ty pe soldering conditi ons ................................................................................ .................223
user?s manual u14801ej3v1ud 20 chapter 1 general 1.1 expanded-specification products and conventional products expanded-specification products and conventional products refer to the following products. expanded-specification produc ts: products with a rank note other than k ? mask rom versions for which orders we re received after december 1, 2001. ? pd78f9076 shipped after january 1, 2002. conventional products: products with rank note k ? products other than the above expanded-specification products. note the rank is indicated by the 5th digit from the left in the lot number marked on the package. lot number o o o o ? year code week code rank expanded-specification products and conventional products differ in operat ing frequency ratings. the differences are shown in table 1-1. table 1-1. differences between expanded-sp ecification products and conventional products guaranteed operating speed (operating frequency) power supply voltage (v dd ) conventional products expanded- specification products 4.5 to 5.5 v 5 mhz (0.4 s) 10 mhz (0.2 s) 3.0 to 5.5 v 5 mhz (0.4 s) 6 mhz (0.33 s) 2.7 to 5.5 v 5 mhz (0.4 s) 5 mhz (0.4 s) 1.8 to 5.5 v 1.25 mhz (1.6 s) 1.25 mhz (1.6 s) remark the parenthesized values indicate the minimum instruction execution time.
chapter 1 general user's manual u14801ej3v1ud 21 1.2 features rom and ram capacity item product name program memory data memory (internal high-speed ram) pd789071, 789071(a) 2 kb pd789072, 789072(a) 4 kb pd789074, 789074(a) mask rom 8 kb pd78f9076 flash memory 16 kb 256 kb minimum instruction execution ti me can be changed from high-speed (0.2 s) to low speed (0.8 s) (at 10.0 mhz, v dd = 4.5 to 5.5 v operation with system clock) i/o ports: 24 serial interface: 1 channel 3-wire serial i/o mode/uart mode: 1 channel timer: 3 channels 16-bit timer: 1 channel 8-bit timer/event counter: 1 channel watchdog timer: 1 channel vectored interrupt sources: 9 supply voltage: v dd = 1.8 to 5.5 v operating ambient temperature: t a = ? 40 to +85 c 1.3 applications small, general home electrical appliances, telephones, etc. 1.4 ordering information part number package quality grade pd789071mc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789072mc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789074mc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789071mc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789072mc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789074mc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd78f9076mc-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd789071mc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd789072mc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd789074mc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd78f9076mc-5a4-a 30-pin plastic sso p (7.62 mm (300)) flash memory remarks 1. indicates rom code suffix. 2. products that have the part numbers su ffixed by "-a" are lead-free products.
chapter 1 general user?s manual u14801ej3v1ud 22 1.5 quality grades part number package quality grade pd789071mc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd789072mc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd789074mc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd78f9076mc-5a4 30-pin plastic ssop (7.62 mm (300)) standard pd789071mc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789072mc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789074mc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789071mc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd789072mc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd789074mc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd78f9076mc-5a4-a 30-pin plasti c ssop (7.62 mm (300)) standard remarks 1. indicates rom code suffix. 2. products that have the part numbers su ffixed by "-a" are lead-free products. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications.
chapter 1 general user?s manual u14801ej3v1ud 23 1.6 pin configuration (top view) 30-pin plastic ssop (7.62 mm (300)) p10 p31/bzo90 ic (v pp ) reset x2 x1 v ss v dd p30/to90 p26/intp2/cpt90 p27/ti80/to80 p25/intp1 p24/intp0 p23/ss20 p22/si20/rxd20 28 27 26 30 29 25 24 23 22 21 20 19 18 16 p11 p12 p13 p14 p15 p00 p01 p02 p03 p05 p04 p06 p07 p20/sck20/asck20 p21/so20/txd20 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 caution connect the ic (internally connected) pin directly to v ss . remark pin connections in parenthes es are intended for the pd78f9076. asck20: asynchronous serial input sck20: serial clock bzo90: buzzer output si20: serial input cpt90: capture trigger i nput so20: serial output ic: internally connected ss20: chip select input intp0 to intp2: external interrupt input ti80: timer input p00 to p07: port 0 to 80, to90: timer output p10 to p15: port 1 txd20: transmit data p20 to p27: port 2 v dd : power supply p30, p31: port 3 v pp : programming power supply reset: reset v ss : ground rxd20: receive data x1, x2: crystal/ceramic oscillator
chapter 1 general user?s manual u14801ej3v1ud 24 1. 7 78k/0s series lineup the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names. 52-pin sio + resistance division method lcd (24 4) 8-bit a/d + internal voltage boosting method lcd (23 4) pd789327 lcd drive 80-pin 80-pin pd789436 pd789446 pd789426 pd789456 pd789417a pd789407a pd789316 pd789467 pd789306 pd789426 with 10-bit a/d pd789860 with enhanced timer function, sio, and expanded rom and ram pd789446 with 10-bit a/d sio + 8-bit a/d + resistance division method lcd (28 4) sio + 8-bit a/d + internal voltage boosting method lcd (15 4) pd789407a with 10-bit a/d sio + 8-bit a/d + internal voltage boosting method lcd (5 4) rc oscillation version of pd789306 sio + internal voltage boosting method lcd (24 4) 64-pin 64-pin 52-pin 64-pin 64-pin 64-pin sio + 10-bit a/d + internal voltage boosting method lcd (28 4) 80-pin sio + 8-bit a/d + resistance division method lcd (28 4) 80-pin pd789479 pd789489 64-pin products under development products in mass production small-scale package, general-purpose applications 78k/0s series 28-pin pd789014 with enhanced timer function and expanded rom and ram on-chip uart and capable of low-voltage (1.8 v) operation pd789074 with subsystem clock added inverter control 44-pin pd789842 on-chip inverter controller and uart pd789146 pd789156 44-pin small-scale package, general-purpose applications and a/d function 44-pin 30-pin 30-pin 30-pin 30-pin pd789124a pd789134a pd789177 pd789167 30-pin 30-pin pd789104a pd789114a pd789167 with 10-bit a/d pd789104a with enhanced timer function pd789124a with 10-bit a/d rc oscillation version of pd789104a pd789104a with 10-bit a/d pd789026 with 8-bit a/d and multiplier added pd789104a with eeprom added pd789146 with 10-bit a/d pd789177y pd789167y y subseries supports smb. usb 88-pin pd789830 pd789835 144-pin uart + dot lcd (40 16) uart + 8-bit a/d + dot lcd (total display outputs: 96) 42-/44-pin 44-pin 30-pin 20-pin 20-pin pd789026 with enhanced timer function rc oscillation version of pd789052 vfd drive 52-pin 64-pin pd789871 on-chip vfd controller (total display outputs: 25) meter control pd789881 uart + resistance division method lcd (26 4) 30-pin pd789074 with enhanced timer function and expanded rom and ram 44-pin pd789800 for pc keyboard. on-chip usb function keyless entry 20-pin 20-pin 30-pin on-chip poc and key return circuit rc oscillation version of pd789860 on-chip bus controller 30-pin pd789850 on-chip can controller pd789074 pd789088 pd789062 pd789014 pd789046 pd789026 pd789052 pd789860 pd789861 pd789862 pd789860 without eeprom tm , poc, and lvi remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same.
chapter 1 general user?s manual u14801ej3v1ud 25 the major functional differences bet ween the subseries are listed below. series for general-purpose a pplications and lcd drive timer v dd function subseries rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min.value remarks pd789046 16 k 1 ch pd789026 4 k to 16 k 1 ch 34 pd789088 16 k to 32 k 3 ch pd789074 2 k to 8 k 1 ch 1 ch 24 pd789014 2 k to 4 k 2 ch ? ? 1 ch ? ? 1 ch (uart: 1 ch) 22 1.8 v ? pd789062 4 k ? 14 rc-oscillation version small- scale package, general- purpose applica- tions pd789052 ? pd789177 ? 8 ch pd789167 16 k to 24 k 3 ch 1 ch 8 ch ? 31 ? pd789156 ? 4 ch pd789146 8 k to 16 k 4 ch ? on-chip eeprom pd789134a ? 4 ch pd789124a 4 ch ? rc-oscillation version pd789114a ? 4 ch small- scale package, general- purpose applica- tions + a/d converter pd789104a 2 k to 8 k 1 ch 1 ch ? 1 ch 4 ch ? 1 ch (uart: 1 ch) 20 1.8 v ? pd789835 24 k to 60 k 6 ch ? 3 ch 37 1.8 v note pd789830 24 k 1 ch ? 1 ch (uart: 1 ch) 30 2.7 v dot lcd supported pd789488 32 k ? 8 ch pd789478 24 k to 32 k 8 ch ? 2 ch (uart: 1 ch) 45 pd789417a ? 7 ch pd789407a 12 k to 24 k 3 ch 1 ch 1 ch 1 ch 7 ch ? 1 ch (uart: 1 ch) 43 1.8 v ? pd789456 ? 6 ch pd789446 6 ch ? 30 pd789436 ? 6 ch pd789426 12 k to 16 k 6 ch 40 pd789316 rc-oscillation version pd789306 8 k to 16 k ? 2 ch (uart: 1 ch) 23 pd789467 1 ch ? 18 lcd drive pd789327 4 k to 24 k 2 ch ? ? ? 1 ch 21 ? note flash memory version: 3.0 v
chapter 1 general user?s manual u14801ej3v1ud 26 series for assp timer v dd function subseries rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min.value remarks usb pd789800 8 k 2 ch ? ? 1 ch ? ? 2 ch (usb: 1 ch) 31 4.0 v ? inverter control pd789842 8 k to 16 k 3 ch note 1 1 ch 1 ch 8 ch ? 1 ch (uart: 1 ch) 30 4.0 v ? on-chip bus controller pd789850 16 k 1 ch 1 ch ? 1 ch 4 ch ? 2 ch (uart: 1 ch) 18 4.0 v ? pd789861 1.8 v rc-oscillation version, on-chip eeprom pd789860 4 k 2 ch ? ? 1 ch ? ? ? 14 keyless entry pd789862 16 k 1 ch 2 ch 1 ch (uart: 1 ch) 22 on-chip eeprom vfd drive pd789871 4 k to 8 k 3 ch ? 1 ch 1 ch ? ? 1 ch 33 2.7 v ? meter control pd789881 16 k 2 ch 1 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 28 2.7 v note 2 ? notes 1. 10-bit timer: 1 channel 2. flash memory version: 3.0 v
chapter 1 general user?s manual u14801ej3v1ud 27 1.8 block diagram v dd v ss ic (v pp ) 78k/0s cpu core rom (flash memory) ram ti80/to80/p27 p00 to p07 port 0 p10 to p15 port 1 p20 to p27 port 2 p30, p31 port 3 cpt90/p26 16-bit timer 90 8-bit timer/event counter 80 watchdog timer serial interface 20 to90/p30 sck20/asck20 /p20 si20/rxd20/p22 so20/txd20/p21 ss20/p23 system control reset x1 x2 interrupt control intp0/p24 intp1/p25 intp2/p26 bzo90/p31 remarks 1. the internal rom capacity varies depending on the product. 2. pin connections in parenthes es are intended for the pd78f9076.
chapter 1 general user?s manual u14801ej3v1ud 28 1.9 overview of functions part number item pd789071 pd789071(a) pd789072 pd789072(a) pd789074 pd789074(a) pd78f9076 mask rom flash memory rom 2 kb 4 kb 8 kb 16 kb internal memory high-speed ram 256 bytes minimum instruction execution time 0.2/0.8 s (@10.0 mhz, v dd = 4.5 to 5.5 v operation with system clock) general-purpose registers 8 bits 8 registers instruction set 16-bit operations bit manipulations (such as set, reset, and test) i/o ports cmos i/o: 24 serial interface switchable between 3-wire serial i/o and uart modes: 1 channel timers 16-bit timer: 1 channel 8-bit timer/event counter: 1 channel watchdog timer: 1 channel timer outputs 2 maskable internal: 5, external: 3 vectored interrupt sources non-maskable internal: 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to + 85c package 30-pin plastic ssop (7.62 mm (300)) the outline of the timers are as follows. 16-bit timer 90 8-bit timer/event counter 80 watchdog timer interval timer ? 1 channel 1 channel note operating mode external event counter ? 1 channel ? timer outputs 1 1 ? pwm outputs ? 1 ? square-wave outputs ? 1 ? buzzer outputs 1 ? ? capture 1 input ? ? function interrupt sources 1 1 2 note the watchdog timer provides a watchdog timer function and interval timer function. use either of the functions.
chapter 1 general user?s manual u14801ej3v1ud 29 1.10 differences between standard quality grade products and (a) products the differences between standard grade products ( pd789071, 789072, 789074) and (a) products ( pd789071(a), 789072(a), 789074(a)) are shown in table 1-2. table 1-2. differences between standard quality grade produc ts and (a) products part number item standard products (a) products quality grade standard special electrical s pecifications refer to chapter 15 elecridal specificat ions (expanded-specification products) and chapter 16 electrical specifications (conventional products)
user?s manual u14801ej3v1ud 30 chapter 2 pin functions 2.1 pin function list (1) port pins pin name i/o function after reset alternate function p00 to p07 i/o port 0 8-bit i/o port input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by setting pull-up resist or option register 0 (pu0). input ? p10 to p15 i/o port 1 6-bit i/o port input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by setting pull-up resist or option register 0 (pu0). input ? p20 sck20/asck20 p21 so20/txd20 p22 si20/rxd20 p23 ss20 p24 intp0 p25 intp1 p26 intp2/cpt90 p27 i/o port 2 8-bit i/o port input/output can be specified in 1-bit units. an on-chip pull-up resistor can be s pecified by setting pull-up resistor option register b2 (pub2). input ti80/to80 p30 to90 p31 i/o port 3 2-bit i/o port input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by setting pull-up resist or option register 0 (pu0). input bzo90
chapter 2 pin functions user?s manual u14801ej3v1ud 31 (2) non-port pins pin name i/o function after reset alternate function intp0 p24 intp1 p25 intp2 input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p26/cpt90 sck20 i/o serial interface (sio10) serial clock input input p20/asck20 si20 input serial interface (sio20) serial data input input p22/rxd20 so20 output serial interface (sio20) serial data output input p21/txd20 ss20 input serial interface chip select i nput input p23 asck20 input serial clock i nput for asynchronous serial interface input p20/sck20 rxd20 input serial data input for asynch ronous serial interface input p22/si20 txd20 output serial data output for asyn chronous serial interface input p21/so20 to90 output 16-bit timer (tm90) output input p30 bzo90 output buzzer output input p31 cpt90 input capture edge input input p26/intp2 to80 output 8-bit timer (tm80) output input p27/ti80 ti80 input external count clock input to 8-bit timer (tm80) input p27/to80 x1 input ? ? x2 ? connecting crystal resonator for system clock oscillation ? ? reset input system reset input input ? v dd ? positive supply voltage ? ? v ss ? ground potential ? ? ic ? internally connected. connect directly to v ss . ? ? v pp ? this pin is used to set the flash memory programming mode and applies a high voltage when a program is written or verified. ? ?
chapter 2 pin functions user?s manual u14801ej3v1ud 32 2.2 description of pin functions 2.2.1 p00 to p07 (port 0) these pins constitute an 8-bit i/o port and can be set to input or output port mode in 1-bit units by using port mode register 0 (pm0). when these pi ns are used as an input port, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (pu0). 2.2.2 p10 to p15 (port 1) these pins constitute a 6-bit i/o port and can be set to i nput or output port mode in 1- bit units by using port mode register 1 (pm1). when these pins are used as an input port, an on-chip pull- up resistor can be used by setting pull- up resistor option register 0 (pu0). 2.2.3 p20 to p27 (port 2) these pins constitute an 8-bit i/o port. in addition, thes e pins provide a function to perform input/output to/from the timer, to input/output the data and clock of the serial interface, and to input the external interrupt. port 2 can be set to the following operation modes in 1-bit units. (1) port mode in port mode, p20 to p27 function as an 8-bit i/o port. po rt 2 can be set to input or output mode in 1-bit units by using port mode register 2 (pm2). for p20 to p27, whether to use on-ch ip pull-up resistors can be specified in 1-bit units by using pu ll-up resistor option register b2 (pub 2), regardless of the setting of port mode register 2 (pm2). (2) control mode in this mode, p20 to p27 function as the timer input/output and the serial interface data and clock input/output. (a) ti80 this is the external clock input pin for the 8-bit timer/event counter 80. (b) to80 this is the timer output pin of the 8-bit timer/event counter 80. (c) intp0 to intp2 these are external interrupt input pins for whic h the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (d) cpt90 this is the capture edge input pin of the 16-bit timer counter 90. (e) si20, so20 this is the serial data i/o pin of the serial interface. (f) sck20 this is the serial clock i/o pin of the serial interface. (g) ss20 this is the chip select input pin of the serial interface.
chapter 2 pin functions user?s manual u14801ej3v1ud 33 (h) rxd20, txd20 these are the serial data i/o pins of the asynchronous serial interface. (i) asck20 this is the serial clock input pin of the asynchronous serial interface. caution when using p20 to p27 as serial interf ace pins, the input/output mode and output latch must be set according to the functions to be used. for details of the setting, see table 9-2 serial interface 20 operation mode settings. 2.2.4 p30, p31 (port 3) these pins constitute a 2-bit i/o port. in addition, thes e pins function as the time r output and the buzzer output. port 3 can be set to the following operation modes in 1-bit units. (1) port mode when this port is used as an input port, an on-chip pu ll-up resistor can be used by setting pull-up resistor option register 0 (pu0). (2) control mode in this mode, p30 and p31 function as the timer output and the buzzer output. (a) to90 this is the output pin of the 16-bit timer 90. (b) bzo90 this is the buzzer output pin of the 16-bit timer 90. 2.2.5 reset an active-low system reset si gnal is input to this pin. 2.2.6 x1, x2 these pins are used to connect a crystal resonator for system clock oscillation. to supply an external clock, input the clo ck to x1 and input the inverted signal to x2. 2.2.7 v dd this pin supplies positive power. 2.2.8 v ss this pin is the ground potential pin.
chapter 2 pin functions user?s manual u14801ej3v1ud 34 2.2.9 v pp ( pd78f9076 only) a high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. handle this pin in either of the following ways. ? connect a 10 k ? pull-down resistor to the pin. ? provide a jumper on the board so t hat the pin is connected to a dedica ted flash programmer in programming mode and to v ss during normal operation. if there is a long wiring length between the v pp pin and the v ss pin or external noise superimposed on the v pp pin, the user program may not run correctly. 2.2.10 ic (mask rom version only) the ic (internally connected) pin is used to set the pd789071, 789072, and 789074 to test mode before shipment. in normal operation mode, directly connect this pin to the v ss pin with as short a wiring length as possible. if a potential difference is generat ed between the ic pin and the v ss pin due to a long wiring length between these pins or external noise superimposed on the ic pin, the user program may not run correctly. ? directly connect the ic pin to the v ss pin. v ss ic keep short
chapter 2 pin functions user?s manual u14801ej3v1ud 35 2.3 pin i/o circuits and recomme nded connection of unused pins the i/o circuit type of each pin and recommended connecti on of unused pins are shown in table 2-1. for the i/o circuit configuration of each type, refer to figure 3-1. table 2-1. types of pin i/o circuits a nd recommended connection of unused pins pin name i/o circuit type i/o re commended connection of unused pins p00 to p07 p10 to p15 5-a p20/sck20/asck20 p21/so20/txd20 p22/si20/rxd20 p23/ss20 input: connect to v dd or v ss via a resistor. output: leave open. p24/intp0 p25/intp1 p26/intp2/cpt90 input: connect to v ss via a resistor. output: leave open. p27/ti80/to80 8-a p30/to90 p31/bzo90 5-a i/o input: connect to v dd or v ss via a resistor. output: leave open. reset 2 input ? ic ? ? connect directly to v ss . v pp connect to a 10 k ? pull-down resistor or directly to v ss .
chapter 2 pin functions user?s manual u14801ej3v1ud 36 figure 2-1. pin i/o circuits schmitt-triggered input with hysteresis characteristics type 2 in type 5-a pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n-ch v ss pull-up enable data output disable v dd p-ch v dd p-ch in/out n-ch v ss type 8-a
user?s manual u14801ej3v1ud 37 chapter 3 cpu architecture 3.1 memory space products in the pd789074 subseries can each access up to 64 kb of memory space. figures 3-1 through 3-4 show the memory maps. figure 3-1. memory map ( pd789071) special function registers 256 8 bits internal high-speed ram 256 8 bits program memory space data memory space program area program area callt table area reserved vector table area internal rom 2,048 8 bits ffffh ff00h feffh fe00h fdffh 07ffh 0080h 007fh 0040h 003fh 0018h 0017h 0000h 0000h 0800h 07ffh
chapter 3 cpu architecture user?s manual u14801ej3v1ud 38 figure 3-2. memory map ( pd789072) special function registers 256 8 bits internal high-speed ram 256 8 bits program memory space data memory space program area program area callt table area reserved vector table area internal rom 4,096 8 bits ffffh ff00h feffh fe00h fdffh 0000h 1000h 0fffh 0fffh 0080h 007fh 0040h 003fh 0018h 0017h 0000h
chapter 3 cpu architecture user?s manual u14801ej3v1ud 39 figure 3-3. memory map ( pd789074) special function registers 256 8 bits internal high-speed ram 256 8 bits program memory space data memory space program area program area callt table area reserved vector table area internal rom 8,192 8 bits ffffh ff00h feffh fe00h fdffh 0000h 2000h 1fffh 1fffh 0080h 007fh 0040h 003fh 0018h 0017h 0000h
chapter 3 cpu architecture user?s manual u14801ej3v1ud 40 figure 3-4. memory map ( pd78f9076) special function registers 256 8 bits internal high-speed ram 256 8 bits program memory space data memory space program area program area callt table area reserved vector table area internal flash memory 16,384 8 bits ffffh ff00h feffh fe00h fdffh 3fffh 0080h 007fh 0040h 003fh 0018h 0017h 0000h 0000h 4000h 3fffh
chapter 3 cpu architecture user?s manual u14801ej3v1ud 41 3.1.1 internal program memory space the internal program memory space stores programs and table data. this space is usually addressed by the program counter (pc). products in the pd789074 subseries provide the following inter nal rom (or flash memory) containing the following capacities. table 3-1. internal rom capacity internal rom part number structure capacity pd789071 2,048 8 bits pd789072 4,096 8 bits pd789074 mask rom 8,192 8 bits pd78f9076 flash memory 16,384 8 bits the following areas are allocated to t he internal program memory space. (1) vector table area the 24-byte area of addresses 0000h to 0017h is reserv ed as a vector table ar ea. this area stores program start addresses to be used when branching by r eset input or interrupt request generation. of a 16-bit program address, the lower 8 bi ts are stored in an even address, and the higher 8 bits are stored in an odd address. table 3-2. vector table vector table address interrupt request vector table address interrupt request 0000h reset input 000ch intsr20/intcsi20 0004h intwdt 000eh intst20 0006h intp0 0014h inttm80 0008h intp1 0016h inttm90 000ah intp2 (2) callt instruction table area the subroutine entry address of a 1-byte call instruction (callt) can be stored in the 64-byte area of addresses 0040h to 007fh. 3.1.2 internal data memory (internal high-speed ram) space the pd789074 subseries provides 256-by te internal high-speed ram. the internal high-speed ram can also be used as a stack memory. 3.1.3 special function register (sfr) area special function registers (sfrs) of on-chip peripheral hardware are allo cated to the area of ff00h to ffffh (see table 3-3 ).
chapter 3 cpu architecture user?s manual u14801ej3v1ud 42 3.1.4 data memory addressing each product of the pd789074 subseries is provided with a wide r ange of addressing modes to make memory manipulation as efficient as possibl e. the data memory area (fe00h to ffffh) can be accessed using a unique addressing mode according to its use, such as a special func tion register (sfr). figures 3-5 through 3-8 illustrate the data memory addressing. figure 3-5. data memory addressing ( pd789071) special function registers (sfrs) 256 8 bits internal high-speed ram 256 8 bits internal rom 2,048 8 bits direct addressing register indirect addressing based addressing sfr addressing short direct addressing reserved ffffh ff20h ff1fh ff00h feffh fe20h fe1fh fe00h fdffh 0800h 07ffh 0000h
chapter 3 cpu architecture user?s manual u14801ej3v1ud 43 figure 3-6. data memory addressing ( pd789072) special function registers (sfrs) 256 8 bits internal high-speed ram 256 8 bits internal rom 4,096 8 bits direct addressing register indirect addressing based addressing sfr addressing short direct addressing reserved ffffh ff20h ff1fh ff00h feffh fe20h fe1fh fe00h fdffh 1000h 0fffh 0000h
chapter 3 cpu architecture user?s manual u14801ej3v1ud 44 figure 3-7. data memory addressing ( pd789074) special function registers (sfrs) 256 8 bits internal high-speed ram 256 8 bits internal rom 8,192 8 bits direct addressing register indirect addressing based addressing sfr addressing short direct addressing reserved ffffh ff20h ff1fh ff00h feffh fe20h fe1fh fe00h fdffh 2000h 1fffh 0000h
chapter 3 cpu architecture user?s manual u14801ej3v1ud 45 figure 3-8. data memory addressing ( pd78f9076) special function registers (sfrs) 256 8 bits internal high-speed ram 256 8 bits internal flash memory 16,384 8 bits direct addressing register indirect addressing based addressing sfr addressing short direct addressing reserved ffffh ff20h ff1fh ff00h feffh fe20h fe1fh fe00h fdffh 4000h 3fffh 0000h
chapter 3 cpu architecture user?s manual u14801ej3v1ud 46 3.2 processor registers the pd789074 subseries provides the followi ng on-chip processor registers. 3.2.1 control registers the control registers have special f unctions to control the program sequenc e statuses and stack memory. the control registers include a pr ogram counter, a program stat us word, and a stack pointer. (1) program counter (pc) the program counter is a 16-bit r egister which holds the address info rmation of the next program to be executed. in normal operation, the pc is automat ically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is execut ed, immediate data or r egister contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-9. program counter configuration 0 15 pc14 pc15 pc pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents ar e automatically stacked upon interr upt request generation or push psw instruction execution and ar e automatically restored upon execution of the reti and pop psw instructions. reset input sets the psw to 02h. figure 3-10. program status word configuration 70 ie z 0 ac 0 0 1 cy psw
chapter 3 cpu architecture user?s manual u14801ej3v1ud 47 (a) interrupt enable flag (ie) this flag controls interrupt request acknowledge operations of the cpu. when ie = 0, the interrupt disabl ed (di) status is set. all inte rrupt requests except non-maskable interrupts are disabled. when ie = 1, the interrupt enabled (ei) status is set. interrupt reques t acknowledgment is controlled with an interrupt mask flag for each interrupt source. this flag is reset to 0 upon di instruction executi on or interrupt acknowledgment and is set to 1 upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set to 1. it is reset to 0 in all other cases. (c) auxiliary carry flag (ac) if the operation result has a carry from bi t 3 or a borrow at bit 3, this flag is set to 1. it is reset to 0 in all other cases. (d) carry flag (cy) this flag stores overflow and underfl ow that have occurred upon add/subtra ct instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruct ion execution.
chapter 3 cpu architecture user?s manual u14801ej3v1ud 48 (3) stack pointer (sp) this is a 16-bit register to hold t he start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-11. stack pointer configuration 0 15 sp14 sp15 sp sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented befor e writing (saving) to the stack me mory and is incremented after reading (restoring) from the stack memory. each stack operation saves/restores dat a as shown in figures 3-12 and 3-13. caution since reset input makes the sp contents unde fined, be sure to initialize the sp before instruction execution. figure 3-12. data to be saved to stack memory figure 3-13. data to be restored from stack memory interrupt psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower half register pairs sp sp _ 2 sp _ 2 call, callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 upper half register pairs reti instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower half register pairs ret instruction pop rp instruction sp pc7 to pc0 upper half register pairs sp + 1 sp sp + 2 sp sp + 1 sp sp + 2 sp sp + 1 sp + 2 sp sp + 3
chapter 3 cpu architecture user?s manual u14801ej3v1ud 49 3.2.2 general-purpose registers the general-purpose register s consist of eight 8-bit registers (x, a, c, b, e, d, l, and h). in addition to each register being used as an 8-bit register , two 8-bit registers can be used in pairs as a 16-bit register (ax, bc, de, and hl). registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). figure 3-14. general-purpo se register configuration (a) absolute names r0 15 0 7 0 16-bit processing 8-bit processing rp3 rp2 rp1 rp0 r1 r2 r3 r4 r5 r6 r7 (b) function names x 15 0 7 0 16-bit processing 8-bit processing hl de bc ax a c b e d l h
chapter 3 cpu architecture user?s manual u14801ej3v1ud 50 3.2.3 special function registers (sfrs) unlike the general-purpose register s, each special function regist er has a special function. the special function registers are alloca ted to the 256-byte area ff00h to ffffh. the special function register s can be manipulated, like t he general-purpose registers, with operation, transfer, and bit manipulation instructions. manipulatable bit units (1 , 8, and 16) differ depending on the special function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe a symbol reserved by the assembler for the 1- bit manipulation instructi on operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe a symbol reserved by the assembler for the 8-bit manipulation instruct ion operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe a symbol reserved by the assembler for the 16- bit manipulation instructi on operand. when specifying an address, describe an even address. table 3-3 lists the special function registers. the meanings of the sym bols in this table are as follows. ? symbol indicates the addresses of the implem ented special function registers. t he symbols shown in this column are reserved words in the assembler, and have already been defined in a header file called "sfrbit.h" in the c compiler. therefore, t hese symbols can be used as instruction operands if an assembler or integrated debugger is used. ? r/w indicates whether the special functi on register can be read or written. r/w: read/write r: read only w: write only ? number of bits manipulated simultaneously indicates the bit units (1, 8, and 16) in which the special function regi ster can be manipulated. ? after reset indicates the status of the special function register when the reset signal is input.
chapter 3 cpu architecture user?s manual u14801ej3v1ud 51 table 3-3. special function registers (1/2) number of bits manipulated simultaneously address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port 0 p0 ? ff01h port 1 p1 ? ff02h port 2 p2 ? ff03h port 3 p3 r/w ? 00h ff16h ff17h 16-bit compare register 90 cr90 note 1 w ? note 2 note 3 ffffh ff18h ff19h 16-bit timer counter 90 tm90 note 1 ? note 2 note 3 0000h ff1ah ff1bh 16-bit capture register 90 tcp90 note 1 r ? note 2 note 3 undefined ff20h port mode register 0 pm0 ? ff21h port mode register 1 pm1 ? ff22h port mode register 2 pm2 ? ff23h port mode register 3 pm3 ? ffh ff32h pull-up resistor option register b2 pub2 ? ff42h watchdog timer clock selection register 2 wdcs ? ? ff48h 16-bit timer mode control register 90 tmc90 ? ff49h buzzer output control register 90 bzc90 r/w ? 00h ff50h 8-bit compare register 80 cr80 w ? ? undefined ff51h 8-bit timer counter 80 tm80 r ? ? ff53h 8-bit timer mode control register 80 tmc80 ? ff70h asynchronous serial interface mode register 20 asim20 r/w ? ff71h asynchronous serial interface status register 20 asis20 r ? ff72h serial operation mode register 20 csim20 ? ff73h baud rate generator control register 20 brgc20 r/w ? ? 00h notes 1. these sfrs are for 16-bit access only. 2. cr90, tm90, and tcp90 are designed only for 16-bit access. in direct addressing, however, 8-bit access can also be performed. 3. 16-bit access is allowed only in short direct addressing.
chapter 3 cpu architecture user?s manual u14801ej3v1ud 52 table 3-3. special function registers (2/2) number of bits manipulated simultaneously address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset transmission shift register 20 txs20 w ? ? ffh ff74h receive buffer register 20 rxb20 sio20 r ? ? undefined ffe0h interrupt request flag register 0 if0 ? ffe1h interrupt request flag register 1 if1 ? 00h ffe4h interrupt mask flag register 0 mk0 ? ffe5h interrupt mask flag register 1 mk1 ? ffh ffech external interrupt mode register 0 intm0 ? ? fff7h pull-up resistor option register 0 pu0 ? fff9h watchdog timer mode register wdtm ? 00h fffah oscillation stabilization time selection register osts ? ? 04h fffbh processor clock control register pcc r/w ? 02h
chapter 3 cpu architecture user?s manual u14801ej3v1ud 53 3.3 instruction address addressing an instruction address is determined by the program counter (p c) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an in struction to be fetched each time another instruction is executed. when a branch instruction is ex ecuted, the branch destination address information is set to the pc to branch by the following addressing (for details of eac h instruction, refer to 78k/0s series instructions user's manual (u11047e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immedi ate data (displacement value: jdis p8) of an instruction code to the start address of the following instruction is transfe rred to the program counter (pc) and branched. the displacement value is treated as signed two's complem ent data (?128 to +127) and bit 7 becomes the sign bit. in other words, the range of branch in relative addressing is betw een ?128 and +127 of the st art address of the following instruction. this function is carried out when the br $addr16 instruct ion or a conditional branch instruction is executed. [illustration] 15 0 pc 15 0 s 15 0 pc + 876 jdisp8 when s = 0, indicates that all bits are "0". ... pc is the start address of the next instruction of a br instruction. when s = 1, indicates that all bits are "1".
chapter 3 cpu architecture user?s manual u14801ej3v1ud 54 3.3.2 immediate addressing [function] immediate data in the instructi on word is transferred to the pr ogram counter (pc) and branched. this function is carried out when the call !addr 16 and br !addr16 instruct ions are executed. call !addr16 and br !addr16 instru ctions can be used to branch to all the memory spaces. [illustration] in case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr.
chapter 3 cpu architecture user?s manual u14801ej3v1ud 55 3.3.3 table indirect addressing [function] the table contents (branch des tination address) of the particular locati on to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are tr ansferred to the program counter (pc) and branched. table indirect addressing is carried out when the callt [addr5] inst ruction is executed. this instruction can be used to branch to all the memory spaces according to the address stored in the me mory table 40h to 7fh. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 0 01 765 10 ta 4?0 instruction code 3.3.4 register addressing [function] the register pair (ax) contents to be specified with an instruction word ar e transferred to the program counter (pc) and branched. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
chapter 3 cpu architecture user?s manual u14801ej3v1ud 56 3.4 operand address addressing the following methods (addressing) are available to s pecify the register and memo ry to undergo manipulation during instruction execution. 3.4.1 direct addressing [function] the memory indicated by immediate data in an instruction word is directly addressed. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !fe00h; when setting !addr16 to fe00h instruction code 0 0 1 0 1 0 0 1 op code 0 0 0 0 0 0 0 0 00h 1 1 1 1 1 1 1 0 feh [illustration] 70 op code addr16 (low) addr16 (high) memory
chapter 3 cpu architecture user?s manual u14801ej3v1ud 57 3.4.2 short direct addressing [function] the memory to be manipulated in the fixed space is dire ctly addressed with the 8-bit data in an instruction word. the fixed space where this addressing is applied is t he 256-byte space fe20h to ff1fh. an internal high- speed ram is mapped at fe20h to feffh and the specia l function registers (sfr ) are mapped at ff00h to ff1fh. the sfr area where short direct addressi ng is applied (ff00h to ff1fh) is a par t of the total sfr area. in this area, ports which are frequently acce ssed in a program and a compare regi ster of the timer counter are mapped, and these sfrs can be manipulated with a small num ber of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effe ctive address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see [illustration] below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh i mmediate data (even address only) [description example] mov fe90h, #50h; when setting saddr to fe90h and the immediate data to 50h instruction code 1 1 1 1 0 1 0 1 op code 1 0 0 1 0 0 0 0 90h (saddr-offset) 0 1 0 1 0 0 0 0 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 8 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0. when 8-bit immediate data is 00h to 1fh, = 1.
chapter 3 cpu architecture user?s manual u14801ej3v1ud 58 3.4.3 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addre ssed with the 8-bit immediat e data in an instruction word. this addressing is applied to the 256-byte spaces ff 00h to ffffh. however, sfrs mapped at ff00h to ff1fh can also be accessed with short direct addressing. [operand format] identifier description sfr special function register name [description example] mov pm0, a; when selecting pm0 for sfr instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
chapter 3 cpu architecture user?s manual u14801ej3v1ud 59 3.4.4 register addressing [function] a general-purpose register is accessed as an operand. the general-purpose register to be acce ssed is specified with t he register specify c ode and functional name in the instruction code. register addressing is carried out when an instruction with the following operand forma t is executed. when an 8-bit register is specified, one of the eight registers is specified wit h 3 bits in the instruction code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl 'r' and 'rp' can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting the c register for r instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 register specify code incw de; when selecting the de register pair for rp instruction code 1 0 0 0 1 0 0 0 register specify code
chapter 3 cpu architecture user?s manual u14801ej3v1ud 60 3.4.5 register indirect addressing [function] the memory is addressed with the contents of the r egister pair specified as an oper and. the register pair to be accessed is specified with t he register pair specify code in the instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting register pair [de] instruction code 0 0 1 0 1 0 1 1 [illustration] 15 0 8 d 7 e 0 7 7 0 a de the contents of addressed memory are transferred memory address specified by register pair de
chapter 3 cpu architecture user?s manual u14801ej3v1ud 61 3.4.6 based addressing [function] 8-bit immediate data is added to the cont ents of the base register, that is, t he hl register pair, and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3.4.7 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automat ically employed when the push, pop, subroutine call, and return instructions are executed or the register is saved/restor ed upon interrupt request generation. stack addressing can be used to access t he internal high-speed ram area only. [description example] in the case of push de instruction code 1 0 1 0 1 0 1 0
user?s manual u14801ej3v1ud 62 chapter 4 port functions 4.1 port functions the pd789074 subseries is provided with the ports shown in figure 4-1. t hese ports enable several types of control. table 4-1 lists the functions of each port. these ports have digital i/o port functions as well as alte rnate functions. for the alternate functions, refer to 2.1 pin function list . figure 4-1. port types port 2 port 3 port 0 port 1 p20 p27 p30 p31 p00 p07 p10 p15
chapter 4 port functions user?s manual u14801ej3v1ud 63 table 4-1. port functions pin name i/o function after reset alternate function p00 to p07 i/o port 0 8-bit i/o port input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by setting pull-up resist or option register 0 (pu0). input ? p10 to p15 i/o port 1 6-bit i/o port input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by setting pull-up resist or option register 0 (pu0). input ? p20 sck20/asck20 p21 so20/txd20 p22 si20/rxd20 p23 ss20 p24 intp0 p25 intp1 p26 intp2/cpt90 p27 i/o port 2 8-bit i/o port input/output can be specified in 1-bit units. an on-chip pull-up resistor can be s pecified by setting pull-up resistor option register b2 (pub2). input ti80/to80 p30 to90 p31 i/o port 3 2-bit i/o port input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by setting pull-up resist or option register 0 (pu0). input bzo90
chapter 4 port functions user?s manual u14801ej3v1ud 64 4.2 port configuration ports include the following hardware. table 4-2. configuration of port parameter configuration control registers port mode registers (pmm: m = 0 to 3) pull-up resistor option register 0 (pu0) pull-up resistor option register b2 (pub2) ports cmos i/o: 24 pull-up resistors software control: 24 4.2.1 port 0 this is an 8-bit i/o port with an output latc h. port 0 can be set to input or out put mode in 1-bit units by using port mode register 0 (pm0). when pins p00 to p07 are used as input port pi ns, on-chip pull-up resistors can be connected in 8-bit units by setting pull- up resistor option register 0 (pu0). reset input sets port 0 to input mode. figure 4-2 shows a block diagram of port 0. figure 4-2. block di agram of p00 to p07 internal bus wr pu0 rd wr port wr pm pu00 output latch (p00 to p07) pm00 to pm07 v dd p-ch p00 to p07 selector pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 4 port functions user?s manual u14801ej3v1ud 65 4.2.2 port 1 this is a 6-bit i/o port with an output latc h. port 1 can be set to input or out put mode in 1-bit units by using port mode register 1 (pm1). when pins p10 to p15 are used as input port pi ns, on-chip pull-up resistors can be connected in 6-bit units by setting pull- up resistor option register 0 (pu0). reset input sets port 1 to input mode. figure 4-3 shows a block diagram of port 1. figure 4-3. block di agram of p10 to p15 internal bus wr pu0 rd wr port wr pm pu01 output latch (p10 to p15) pm10 to pm15 v dd p-ch p10 to p15 selector pu0: pull-up resistor option register 0 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 4 port functions user?s manual u14801ej3v1ud 66 4.2.3 port 2 this is an 8-bit i/o port with an output latc h. port 2 can be set to input or out put mode in 1-bit units by using port mode register 2 (pm2). for pins p20 to p27, on-chip pull-up resistors can be connected in 1-bit units by setting pull- up resistor option register b2 (pub2). port 2 is also used for external interr upt input, serial interface i/o, and timer i/o. reset input sets port 2 to input mode. figures 4-4 through 4-7 show block diagrams of port 2. caution when using the pins of port 2 for the seria l interface, the i/o and output latches must be set according to the function to be used. for deta ils of the settings, see table 9-2 operation mode settings of serial interface 20. figure 4-4. block diagram of p20 internal bus v dd p-ch p20/asck20/ sck20 wr pub2 rd wr port wr pm pub20 alternate function output latch (p20) pm20 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 4 port functions user?s manual u14801ej3v1ud 67 figure 4-5. block diagram of p21 internal bus v dd p-ch p21/txd20/ so20 wr pub2 rd wr port wr pm pub21 output latch (p21) pm21 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 4 port functions user?s manual u14801ej3v1ud 68 figure 4-6. block di agram of p22 to p26 internal bus v dd p-ch p22/rxd20/si20 p23/ss20 p24/intp0 p25/intp1 p26/intp2/cpt90 wr pub2 rd wr port wr pm pub22 to pub26 alternate function output latch (p22 to p26) pm22 to pm26 selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 4 port functions user?s manual u14801ej3v1ud 69 figure 4-7. block diagram of p27 internal bus v dd p-ch p27/ti80/to80 wr pub2 rd wr port wr pm pub27 alternate function output latch (p27) alternate function pm27 selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 4 port functions user?s manual u14801ej3v1ud 70 4.2.4 port 3 this is a 2-bit i/o port with an output latc h. port 3 can be set to input or out put mode in 1-bit units by using port mode register 3 (pm3). when p30 and p 31 are used as input port pins, on-chip pull-up resistors can be connected in 2-bit units by setting pull-up resi stor option register 0 (pu0). port 3 is also used for timer output and buzzer output. reset input sets port 3 to input mode. figure 4-9 shows a block diagram of port 3. figure 4-8. block diagram of p30 and p31 internal bus wr pu0 rd wr port wr pm pu03 output latch (p30, p31) pm30, pm31 alternate function v dd p-ch p30/to90 p31/bzo90 selector pu0: pull-up resistor option register 0 pm: port mode register rd: port 3 read signal wr: port 3 write signal
chapter 4 port functions user?s manual u14801ej3v1ud 71 4.3 port function control registers the following two types of register s are used to control the ports. port mode registers (pm0 to pm3) pull-up resistor option registers (pu0 and pub2) (1) port mode registers (pm0 to pm3) the port mode registers separately set eac h port bit to either input or output. each port mode register is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets the port mode registers to ffh. when port pins are used for alternate functions, the corresponding port mode regist er and output latch must be set or reset as described in table 4-3. caution when port 2 is acting as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as the input for an external interrupt. to use port 2 in output mode, therefore, the interr upt mask flag must be set to 1 in advance. figure 4-9. format of port mode register pmmn 0 output mode (output buffer on) input mode (output buffer off) 1 pmn pin input/output mode selection (m = 0 to 3, n = 0 to 7) pm07 pm06 pm05 pm04 pm03 pm02 pm01 pm00 pm0 76 54 symbol address after reset r/w ff20h ffh r/w 3210 1 1 pm15 pm14 pm13 pm12 pm11 pm10 pm1 ff21h ffh r/w pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 ff22h ffh r/w 1 1 1 1 1 1 pm31 pm30 pm3 ff23h ffh r/w
chapter 4 port functions user?s manual u14801ej3v1ud 72 table 4-3. port mode register and output latch settings for us ing alternate functions alternate function pin name name input/output pm p p24 intp0 input 1 p25 intp1 input 1 intp2 input 1 p26 cpt90 input 1 ti80 input 1 p27 to80 output 0 0 p30 to90 output 0 0 p31 bzo90 output 0 0 caution when using the pins of port 2 for the ser ial interface, the i/o or output latch must be set according to the function to be used. for de tails of the settings, see table 9-2 operation mode settings of serial interface 20. remark : don't care pm : port mode register p : port output latch (2) pull-up resistor option register 0 (pu0) pull-up resistor option register 0 (pu0 ) sets whether an on-chip pull-up resist or is used for ports 0, 1, and 3. for ports specified by pu0 to use on-chip pull-up resi stors, pull-up resistors can be internally used only for the bits set to input mode. no on-chip pull-up re sistors can be used for the bits set to output mode regardless of the setting of pu0. on-chip pull-up re sistors also cannot be used when the pins are used as the alternate-function output pins. pu0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears pu0 to 00h. figure 4-10. format of pull-up resistor option register 0 pu0m 0 1 pm on-chip pull-up resistor selection (m = 0, 1, 3) on-chip pull-up resistor is not used. on-chip pull-up resistor is used. 0 0 0 0 pu03 0 pu01 pu00 pu0 76 54 symbol address after reset r/w fff7h 00h r/w <3> 2 <1> <0> caution bits 2 and 4 to 7 must all be set to 0.
chapter 4 port functions user?s manual u14801ej3v1ud 73 (3) pull-up resistor option register b2 (pub2) this register specifies whether the on-chip pull-up resistor connected to eac h pin of port 2 is used. the pins for which use of an on-chip pull-up resistor is specif ied by pub2 can use a pull-up register internally, regardless of the setting of the port mode register. pub2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears pub2 to 00h. figure 4-11. format of pull-up resistor option register b2 pub2n 0 1 p2n on-chip pull-up resistor selection (n = 0 to 7) on-chip pull-up resistor is not used. on-chip pull-up resistor is used. pub27 pub26 pub25 pub24 pub23 pub22 pub21 pub20 pub2 <7> <6> <5> <4> symbol address after reset r/w ff32h 00h r/w <3> <2> <1> <0>
chapter 4 port functions user?s manual u14801ej3v1ud 74 4.4 operation of port functions the operation of a port differs depending on whether the port is set to input or output mode, as described below. 4.4.1 writing to i/o port (1) in output mode a value can be written to the output la tch of a port by using a transfer inst ruction. the cont ents of the output latch can be output from the pins of the port. once data is written to the output latch, it is re tained until new data is wri tten to the output latch. (2) in input mode a value can be written to the output latc h by using a transfer instruction. however, the status of the port pin is not changed because the out put buffer is off. once data is written to the output latch, it is re tained until new data is wri tten to the output latch. caution a 1-bit memory manipulation instruction is executed to manipulate one bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of a port consisti ng both of inputs and outputs, therefore, the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined. 4.4.2 reading from i/o port (1) in output mode the contents of the out put latch can be read by using a transfer inst ruction. the content s of the output latch are not changed. (2) in input mode the status of a pin can be read by using a transfer instruction. the contents of the output latch are not changed. 4.4.3 arithmetic operation of i/o port (1) in output mode an arithmetic operation can be performed with the contents of the output latch. the re sult of the operation is written to the output latch. the contents of the out put latch are output from the port pins. once data is written to the output latch, it is re tained until new data is wri tten to the output latch. (2) in input mode the contents of the output latch become undefined. however, the status of the pin is not changed because the output buffer is off. caution a 1-bit memory manipulation instruction is executed to manipulate one bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of a port consisti ng both of inputs and outputs, therefore, the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined.
user?s manual u14801ej3v1ud 75 chapter 5 clock generator 5.1 clock generator functions the clock generator generates the clock to be s upplied to the cpu and peripheral hardware. ? expanded-specification products the system oscillator oscillates a frequency of 1.0 to 10.0 mhz. oscillation can be stopped by executing the stop instruction. ? conventional products the system oscillator oscillates a frequency of 1.0 to 5.0 mhz. oscillation can be stopped by executing the stop instruction. 5.2 clock generator configuration the clock generator includes the following hardware. table 5-1. configuration of clock generator item configuration control register processor cl ock control register (pcc) oscillator crystal/ceramic oscillator figure 5-1. block diag ram of clock generator prescaler system clock oscillator f x prescaler standby controller wait controller cpu clock (f cpu ) stop f x 2 2 clock to peripheral hardware pcc1 internal bus processor clock control register (pcc) x1 x2 selector
chapter 5 clock generator user?s manual u14801ej3v1ud 76 5.3 clock generator control register the clock generator is controll ed by the following register. ? processor clock control register (pcc) (1) processor clock control register (pcc) pcc selects the cpu clock and the division ratio. pcc is set with a 1-bit or 8-bit me mory manipulation instruction. reset input sets pcc to 02h. figure 5-2. format of processo r clock control register minimum instruction execution time: 2/f cpu cpu clock (f cpu ) selection at f x = 10.0 mhz note at f x = 5.0 mhz pcc1 0 1 f x f x /2 2 0.2 s 0.8 s 0.4 s 1.6 s 0 0 0 0 0 0 pcc1 0 pcc 76 54 symbol address after reset r/w fffbh 02h r/w 3210 note expanded-specificati on products only. caution bits 0 and 2 to 7 must all be set to 0. remark f x : system clock oscillation frequency
chapter 5 clock generator user?s manual u14801ej3v1ud 77 5.4 system clock oscillators 5.4.1 system clock oscillator the system clock oscillator is oscillat ed by the crystal or ceramic resonator (5.0 mhz typ.) connected across the x1 and x2 pins. an external clock can also be input to the circuit. in th is case, input the clock signal to the x1 pin, and input the inverted signal to the x2 pin. figure 5-3 shows the external circui t of the system clock oscillator. figure 5-3. external circuit of system clock oscillator (a) crystal or ceramic osc illation (b) external clock v ss x1 x2 crystal or ceramic resonator external clock x1 x2 caution when using the system clo ck oscillator, wire as follows in th e area enclosed by the broken lines in figure 5-3 to avoid an adver se effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator.
chapter 5 clock generator user?s manual u14801ej3v1ud 78 5.4.2 examples of incorr ect resonator connection figure 5-4 shows an example of incorrect resonator connections. figure 5-4. examples of incorr ect resonator connection (1/2) (a) wiring too long (b) crossed signal line v ss x1 x2 v ss x1 x2 portn (n = 0 to 3) (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 high current v ss x1 ab c p mn v dd high current x2
chapter 5 clock generator user?s manual u14801ej3v1ud 79 figure 5-4. examples of incorr ect resonator connection (2/2) (e) signal is fetched v ss x1 x2 5.4.3 frequency divider the frequency divider divides the system clock oscillator output (f x ) and generates clocks.
chapter 5 clock generator user?s manual u14801ej3v1ud 80 5.5 clock generator operation the clock generator generates the following clocks and controls the oper ation modes of the cpu, such as standby mode. ? system clock f x ? cpu clock f cpu ? clock to peripheral hardware the operation of the clock gener ator is determined by the processor clo ck control register (pcc) as follows. (a) the slow mode (0.8 s: at 10.0 mhz operation/1.6 s: at 5.0 mhz operation) of the system clock is selected when the reset signal is generated (pcc = 02h). while a low level is input to the reset pin, oscillation of the system clock is stopped. (b) two types of minimum instruction execution time (0.2 s, 0.8 s: at 10.0 mhz operation/0.4 s, 1.6 s: at 5.0 mhz operation) can be sele cted by the pcc setting. (c) two standby modes, stop and halt, can be used. (d) the clock for the peripheral hardw are is generated by dividing the frequency of the system clo ck. therefore, the peripheral hardware stops when the system clock stops (except for an external input clock).
chapter 5 clock generator user?s manual u14801ej3v1ud 81 5.6 changing setting of cpu clock 5.6.1 time required fo r switching cpu clock the cpu clock can be switched by using bit 1 (pcc1) of the processor clock control register (pcc). actually, the specified clock is not switched immediately after the setti ng of pcc has been changed; old clock is used for the duration of several instructions after that (see table 5-2 ). table 5-2. maximum time re quired for switching cpu clock set value before switching set value after switching pcc1 pcc1 pcc1 0 1 0 4 clocks 1 2 clocks remark two clocks is the minimum instruction execut ion time of the cpu clock before switching. 5.6.2 switching cpu clock the following figure illustrates how the cpu clock is switched. figure 5-5. switching between system clock and cpu clock cpu clock reset v dd f x f x slow operation fast operation wait (3.28 ms: @ 10.0 mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on pow er application. the effect of resetting is released when the reset pin is later made high, and the system clock starts oscillati ng. at this time, the oscillation stabilization time (2 15 /f x ) is automatically secured. after that, the cpu starts instruction execut ion at the slow speed of the system clock (0.8 s: @10.0 mhz operation/1.6 s: @5.0 mhz operation). <2> after the time required for the v dd voltage to rise to the level at which the cpu can operate at the high speed has elapsed, the processor clock control register (pcc) is rewri tten so that the high-speed operation can be selected.
user?s manual u14801ej3v1ud 82 chapter 6 16-bit timer 90 6.1 functions of 16-bit timer 90 16-bit timer 90 has the following functions. ? timer interrupt ? timer output ? buzzer output ? count value capture (1) timer interrupt an interrupt is generated when the c ount value and compare value match. (2) timer output timer output can be controlled when the count value and compare value match. (3) buzzer output buzzer output can be controlled by software. (4) count value capture the count value of 16-bit timer count er 90 (tm90) is latched into a capt ure register in synchronization with the capture trigger and retained. 6.2 configuration of 16-bit timer 90 16-bit timer 90 includes the following hardware. table 6-1. configuration of 16-bit timer 90 item configuration timer counter 16 bits 1 (tm90) registers compare register: 16 bits 1 (cr90) capture register: 16 bits 1 (tcp90) timer outputs 1 (to90) control registers 16-bit timer mode control register 90 (tmc90) buzzer output control register 90 (bzc90) port mode register 3 (pm3) port 3 (p3)
chapter 6 16-bit timer 90 user?s manual u14801ej3v1ud 83 figure 6-1. block diag ram of 16-bit timer 90 f x /2 2 f x /2 4 f x /2 6 16-bit timer mode control register 90 (tmc90) ctp90/intp2/ p26 edge detector 16-bit capture register 90 (tcp90) 16-bit counter read buffer write controller f x /2 cpu clock write controller match internal bus internal bus f/f ovf tod90 to90/p30 inttm90 bzo90/p31 buzzer output control register 90 (bzc90) bcs902 bcs901 / 3 bcs900 bzoe90 p30 output latch pm30 p31 output latch pm31 16-bit timer counter 90 (tm90) tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 selector selector 16-bit compare register 90 (cr90)
chapter 6 16-bit timer 90 user?s manual u14801ej3v1ud 84 (1) 16-bit compare register 90 (cr90) the value specified in cr90 is com pared with the count in 16-bit timer c ounter 90 (tm90). if they match, an interrupt request (inttm90) is issued by cr90. cr90 is set with an 8-bit or 16-bit memory manipulati on instruction. any value from 0000h to ffffh can be set. reset input sets cr90 to ffffh. cautions 1. cr90 is designed to be manipulated wit h a 16-bit memory manipulation instruction. it can also be manipulated with 8-bit memory manipulation instructions, however. when an 8-bit memory manipulation instruction is used to set cr90, it must be accessed by direct addressing. 2. to re-set cr90 during a count operation, it is necessary to disable interrupts in advance, using interrupt mask fl ag register 1 (mk1). it is also necessary to disable inversion of the timer output data, using 16-bi t timer mode control register 90 (tmc90). if cr90 is rewritten with interrupts enab led, an interrupt request may be issued immediately at the point of rewrite. (2) 16-bit timer counter 90 (tm90) tm90 is used to count the number of pulses. the contents of tm90 are read with an 8-bit or 16-bit memory manipulation instruction. reset input clears tm90 to 0000h. cautions 1. the count becomes undefined when stop mode is released, because the count operation is performed befo re oscillation stabilizes. 2. tm90 is designed to be manipulated with a 16-bit memory manipulation instruction. it can also be manipulated with 8-bit memory manipulation instructions, however. when an 8-bit memory instruction is used to manipulate tm90, it must be accessed by direct addressing. 3. when an 8-bit memory ma nipulation instruction is used to manipulate tm90, the lower and higher bytes must be read as a pair, in that order. (3) 16-bit capture register 90 (tcp90) tcp90 captures the contents of 16-bit timer counter 90 (tm90). this register is set with an 8-bit or 16-bit memory manipulation instruction. reset input makes tcp90 undefined. caution tcp90 is designed to be manipulated with a 16-bit memory manipulation instruction. it can also be manipulated with 8-bit memory manipulation instructions, however. when an 8-bit memory manipulation instruction is u sed to manipulate tcp 90, it must be accessed by direct addressing. (4) 16-bit counter read buffer 90 this buffer is used to latch and hold the count for 16-bit timer counter 90 (tm90).
chapter 6 16-bit timer 90 user?s manual u14801ej3v1ud 85 6.3 control registers of 16-bit timer 90 the following four registers are used to control 16-bit timer 90. ? 16-bit timer mode control register 90 (tmc90) ? buzzer output control register 90 (bzc90) ? port mode register 3 (pm3) ? port 3 (p3) (1) 16-bit timer mode control register 90 (tmc90) 16-bit timer mode control register 90 (tmc90) controls the setting of t he count clock, c apture edge, etc. tmc90 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc90 to 00h.
chapter 6 16-bit timer 90 user?s manual u14801ej3v1ud 86 figure 6-2. format of 16-bit timer mode control register 90 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 symbol address after reset r/w ff48h 00h r/w note 1 5 <6> 4321<0> 7 tof90 0 1 overflow flag setting reset or cleared by software set when the 16-bit timer overflows cpt901 0 0 1 1 capture edge selection cpt900 0 1 0 1 capture operation disabled captured at the rising edge at the cpt90 pin captured at the falling edge at the cpt90 pin captured at both the rising and falling edges at the cpt90 pin toc90 0 1 timer output data inversion control inversion disabled inversion enabled tcl901 0 0 1 1 16-bit timer counter 90 count clock (fcl) selection at f x = 10.0 mhz note 2 at f x = 5.0 mhz tcl900 0 1 0 1 toe90 0 1 16-bit timer counter output control output disabled (port mode) output enabled tod90 0 1 timer output data timer output of 0 timer output of 1 f x /2 2 f x /2 6 f x /2 4 setting prohibited 2.5 mhz 156 khz 625 khz 1.25 mhz 78.1 khz 313 khz notes 1. bit 7 is read-only. 2. expanded-specificati on products only. caution disable interrupts in ad vance using interrupt mask flag re gister 1 (mk1) when changing the data of tcl901 and tcl900. also, preven t the timer output data from being inverted by setting toc90 to 1. remark f x : system clock oscillation frequency
chapter 6 16-bit timer 90 user?s manual u14801ej3v1ud 87 (2) buzzer output control register 90 (bzc90) this register selects a buzzer frequency based on fcl se lected with the count clo ck select bits (tcl901 and tcl900), and controls the out put of a square wave. bzc90 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears bzc90 to 00h. figure 6-3. format of buzzer output control register 90 bzoe90 buzzer port output control disables buzzer port output. enables buzzer port output. 0 1 0 0 0 0 bcs902 bcs901 bcs900 bzoe90 bzc90 symbol address after reset r/w ff49h 00h r/w 6 754 bcs902 bcs901 bcs900 buzzer frequency f x = 10.0 mhz operation note f x = 5.0 mhz operation 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3 21 <0> fcl/2 4 fcl/2 5 fcl/2 8 fcl/2 9 fcl/2 10 fcl/2 11 fcl/2 12 fcl/2 13 fcl = f x /2 2 156 khz 78.1 khz 9.77 khz 4.88 khz 2.44 khz 1.22 khz 610 hz 305 hz fcl = f x /2 6 9.77 khz 4.88 khz 610 hz 305 hz 153 hz 76.3 hz 38.1 hz 19.1 hz fcl = f x /2 4 39.1 khz 19.5 khz 2.44 khz 1.22 khz 610 hz 305 hz 153 hz 76.3 hz fcl = f x /2 2 78.1 khz 39.1 khz 4.88 khz 2.44 khz 1.22 khz 610 hz 305 hz 153 hz fcl = f x /2 6 4.88 khz 2.44 khz 305 hz 153 hz 76.3 hz 38.1 hz 19.1 hz 9.54 hz fcl = f x /2 4 19.5 khz 9.77 khz 1.22 khz 610 hz 305 hz 153 hz 76.3 hz 38.1 hz note expanded-specificati on products only. caution bits 4 to 7 must all be set to 0. remarks 1. f x : system clock oscillation frequency 2. fcl: count clock frequency of 16-bit timer 90.
chapter 6 16-bit timer 90 user?s manual u14801ej3v1ud 88 (3) port mode register 3 (pm3) pm3 is used to set each bit of port 3 to input or output. when pin p30/to90 is used for timer output, reset the output latch of p30 and pm30 to 0; when pin p31/bzo90 is used for buzzer output, reset the output latch of p31 and pm31 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 6-4. format of port mode register 3 pm3n p3n pin i/o mode (n = 0, 1) output mode (output buffer on) input mode (output buffer off) 0 1 1 1 1 1 1 1 pm31 pm30 pm3 symbol address after reset r/w ff23h ffh r/w 6 754 3 21 0
chapter 6 16-bit timer 90 user?s manual u14801ej3v1ud 89 6.4 operation of 16-bit timer 90 6.4.1 operation as timer interrupt 16-bit timer 90 can generate interrupts repeatedly each time the free-running counter val ue reaches the value set to cr90. since this counter is not cleared and holds the count even after an inte rrupt is generated, the interval time is equal to one cycle of the count clock set in tcl901 and tcl900. to operate 16-bit timer 90 as a timer interrupt, the following settings are required. ? set the count value in cr90 ? set 16-bit timer mode control register 90 (tmc90) as shown in figure 6-5. figure 6-5. settings of 16-bit timer mode cont rol register 90 for timer interrupt operation ? 0/1 0/1 0/1 0/1 0/1 0/1 0/1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 setting of count clock (see table 6-2 ) caution if both the cpt901 and cpt900 flags are set to 0, the capture operation is disabled. when the count value of 16-bit time r counter 90 (tm90) matches the va lue set in cr90, counting of tm90 continues and an interrupt request signal (inttm90) is generated. table 6-2 shows the interval time, and figure 6-6 s hows the timing of the ti mer interrupt operation. caution perform the following processing when rewriting cr90 during a count operation. <1> disable interrupts (tmmk90 (bit 1 of inte rrupt mask flag register 1 (mk1)) = 1). <2> disable inversion control of timer output data (toc90 = 0). if cr90 is rewritten with interrupts enabled, an interrupt request may be issued immediately at the point of rewrite. table 6-2. interval time of 16-bit timer 90 count clock interval time tcl901 tcl900 at f x = 10.0 mhz operation note at f x = 5.0 mhz operation at f x = 10.0 mhz operation note at f x = 5.0 mhz operation 0 0 2 2 /f x 0.4 s 0.8 s 2 18 /f x 26.2 ms 52.4 ms 0 1 2 6 /f x 6.4 s 12.8 s 2 22 /f x 419 ms 839 ms 1 0 2 4 /f x 1.6 s 3.2 s 2 20 /f x 105 ms 210 ms 1 1 setting prohibited note expanded-specification products only. remark f x : system clock oscillation frequency
chapter 6 16-bit timer 90 user?s manual u14801ej3v1ud 90 figure 6-6. timing of timer interrupt operation cr90 tm90 count value count clock inttm90 to90 tof90 nn n nn t 0000h n ffffh n 0000h 0001h 0001h interrupt acknowledgment interrupt acknowledgment overflow flag set remark n = 0000h to ffffh
chapter 6 16-bit timer 90 user?s manual u14801ej3v1ud 91 6.4.2 operation as timer output 16-bit timer 90 can invert the timer output repeatedly each time the free-running counter va lue reaches the value set to cr90. since this counter is not cleared and holds the count even after the timer output is inverted, the interval time is equal to one cycle of the count clock set in tcl901 and tcl900. to operate 16-bit timer 90 as a timer out put, the following settings are required. ? set p30 to output mode (pm30 = 0). ? reset the output latch of p30 to 0. ? set the count value in cr90. ? set 16-bit timer mode control register 90 (tmc90) as shown in figure 6-7. figure 6-7. settings of 16-bit timer mode c ontrol register 90 for timer output operation ? 0/1 0/1 0/1 1 0/1 0/1 1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 setting of count clock (see table 6-2 ) inversion enable of timer output data to90 output enable caution if both the cpt901 and cpt900 flags are set to 0, the capture operation is disabled. when the count value of 16-bit timer c ounter 90 (tm90) matches the value set in cr90, the output status of the to90/p30 pin is inverted. this enables timer output. at that time, the tm 90 count continues and an interrupt request signal (inttm90) is generated. figure 6-8 shows the timing of time r output (see table 6-2 for the interval time of 16-bit timer 90). figure 6-8. timer output timing cr90 tm90 count value count clock inttm90 tof90 nn n nn t 0000h n ffffh n 0000h 0001h 0001h to90 note interrupt acknowledgment interrupt acknowledgment overflow flag set note the to90 initial value becomes low level during output enable (toe90 = 1). remark n = 0000h to ffffh
chapter 6 16-bit timer 90 user?s manual u14801ej3v1ud 92 6.4.3 capture operation the capture operation cons ists of latching the count value of 16-bit time r counter 90 (tm90) into a capture register in synchronization with a capture tri gger, and retaining the count value. set tmc90 as shown in figure 6-9 to allow 16- bit timer 90 to start the capture operation. figure 6-9. settings of 16-bit timer mode control register 90 for capture operation ? 0/1 0/1 0/1 0/1 0/1 0/1 0/1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 count clock selection capture edge selection (see table 6-3 ) 16-bit capture register 90 (tcp90) st arts a capture operation after the cp t90 capture trigger edge is detected, and latches and retains the count value of 16-bit timer count er 90. tcp90 fetches the count value within 2 clocks and retains the count value until the next capture edge detection. table 6-3 and figure 6-10 show the se ttings of the capture edge and captur e operation timing, respectively. table 6-3. settings of capture edge cpt901 cpt900 capture edge selection 0 0 capture operation disabled 0 1 cpt90 pin rising edge 1 0 cpt90 pin falling edge 1 1 cpt90 pin both edges caution because tcp90 is rewritten when a capture trigger edge is detected during a tcp90 read, disable the capture trigger edge detection during a tcp90 read. figure 6-10. capture operation timing ( with both edges of cpt90 pin specified) count clock tm90 count read buffer tcp90 cpt90 0000h 0000h 0001h 0001h undefined n n n m ? 1 m m m capture start capture start capture edge detection capture edge detection remark n = 0000h to ffffh m = 0000h to ffffh
chapter 6 16-bit timer 90 user?s manual u14801ej3v1ud 93 6.4.4 16-bit timer counter 90 readout the count value of 16-bit timer c ounter 90 (tm90) is read out with a 16-bit manipulation instruction. tm90 readout is performed through a counter read buffer. the counter read buffe r latches the tm90 count value. the buffer operation is then held pending at the cpu clock falling edge after the read signal of the tm90 lower byte rises and the count value is retained. the counter read buffer value at the retention state can be read out as the count value. cancellation of the pending state is performed at the cpu clock falling edge after the read signal of the tm90 higher byte falls. reset input clears tm90 to 0000h and tm90 re sumes counting in the free-running mode. figure 6-11 shows the timing of 16-bit timer counter 90 readout. cautions 1. the count value after releasing th e stop mode becomes undefined because the count operation is executed during the oscillation stabilization time. 2. though tm90 is designed for a 16-bit transfer in struction, an 8-bit tr ansfer instruction can also be used. when using an 8-bit transfer instru ction, execute it by direct addressing. 3. when using an 8-bit transfer instruction, execute in the order from the lower byte to the higher byte in pairs. if only the lower byte is read, the pe nding state of the counter read buffer is not canceled, and if only the higher byte is read, an undefined count value is read. figure 6-11. 16-bit timer counter 90 readout timing cpu clock count clock tm90 count read buffer tm90 read signal 0000h 0000h 0001h 0001h n n n + 1 read signal latch prohibited period remark n = 0000h to ffffh
chapter 6 16-bit timer 90 user?s manual u14801ej3v1ud 94 6.4.5 buzzer output operation the buzzer frequency is set using buzzer output control register 90 (bzc90) based on the count clock selected with tcl901 and tcl900 of tmc90 (source clock). a s quare wave of the set buzzer frequency is output. table 6-4 shows the buzzer frequency. to operate 16-bit timer 90 as a buzzer out put, the following settings are required. ? set p31 to output mode (pm31 = 0). ? reset output latch of p31 to 0. ? set a count clock by using tcl901 and tcl900. ? set bzc90 as shown in figure 6-12. figure 6-12. settings of buzzer output cont rol register 90 for buzzer output operation 0 0 0 0 0/1 0/1 0/1 1 bcs902 bcs901 bcs900 bzoe90 bzc90 setting of buzzer frequency (see table 6-4 ) enables buzzer output table 6-4. buzzer frequency of 16-bit timer 90 buzzer frequency f x =10.0 mhz operation note f x = 5.0 mhz operation bcs902 bcs901 bcs900 fcl = f x /2 2 fcl = f x /2 6 fcl = f x /2 4 fcl = f x /2 2 fcl = f x /2 6 fcl = f x /2 4 0 0 0 fcl/2 4 156 khz 9.77 khz 39.1 khz 78.1 khz 4.88 khz 19.5 khz 0 0 1 fcl/2 5 78.1 khz 4.88 khz 19.5 khz 39.1 khz 2.44 khz 9.77 khz 0 1 0 fcl/2 8 9.77 khz 610 hz 2.44 khz 4.88 khz 305 hz 1.22 khz 0 1 1 fcl/2 9 4.88 khz 305 hz 1.22 khz 2.44 khz 153 hz 610 hz 1 0 0 fcl/2 10 2.44 khz 153 hz 610 hz 1.22 khz 76.3 hz 305 hz 1 0 1 fcl/2 11 1.22 khz 76.3 hz 305 hz 610 hz 38.1 hz 153 hz 1 1 0 fcl/2 12 610 hz 38.1 hz 153 hz 305 hz 19.1 hz 76.3 hz 1 1 1 fcl/2 13 305 hz 19.1 hz 76.3 hz 153 hz 9.54 hz 38.1 hz note expanded-specificati on products only. remark f x : system clock oscillation frequency
chapter 6 16-bit timer 90 user?s manual u14801ej3v1ud 95 6.5 notes on using 16-bit timer 90 6.5.1 restrictions on rewrit ing 16-bit compare register 90 (1) when rewriting the compare regi ster (cr90), be sure to disable interrupts (tmmk90 = 1), and disable inversion control of timer output (toc90 = 0) first. if cr90 is rewritten with interrupts enabled, an interr upt request may be generated at the point of rewrite. (2) the interval time may be double the intended time depending on the timing at whic h the compare register (cr90) is rewritten. likewise, the timer output waveform may be shorter or double the intended output. to avoid this, rewrite usi ng one of the following procedures. rewriting by 8-bit access <1> disable interrupts (tmmk90 = 1), and disable in version control of timer output (toc90 = 0) <2> rewrite the higher byte of cr90 (16 bits) first <3> next, rewrite the lower byte of cr90 (16 bits) <4> clear the interrupt request flag (tmif90) <5> after more than half the cycle of the count clock has passed from the start of the interrupt, enable timer interrupts and timer output inversion (when count clock = 64/f x , cpu clock = f x ) tm90_vct: set1 tmmk90 ;timer interrupt disable (6 clocks) clr1 tmc90.3 ;timer output inversion disable (6 clocks) mov a,#xxh ;higher byte rewrite value setting (6 clocks) mov !0ff17h,a ;cr90 higher byte rewriting (8 clocks) mov a,#yyh ;lower byte rewrite value setting (6 clocks) mov !0ff16h,a ;cr90 lower byte rewriting (8 clocks) clr1 tmif90 ;interrupt request flag clearing (6 clocks) clr1 tmmk90 ;timer interrupt enable (6 clocks) set1 tmc90.3 ;timer output inversion enable note this is because the inttm90 signal is set to the high level for a period of half the cycle of the count clock after an interrupt is generated, so the output will be inverted if toc90 is set to 1 during this period. more than 32 clocks in total note
chapter 6 16-bit timer 90 user?s manual u14801ej3v1ud 96 rewriting by 16-bit access <1> disable interrupts (tmmk90 = 1), and disable in version control of timer output (toc90 = 0) <2> rewrite cr90 (16 bits) <3> wait for more than one cycle of the count clock <4> clear the interrupt request flag (tmif90) <5> enable timer interrupts and timer output inversion (when count clock = 64/f x , cpu clock = f x ) tm90_vct: set1 tmmk90 ;timer interrupt disable clr1 tmc90.3 ;timer output inversion disable movw ax,#xxyyh ;cr90 rewrite value setting movw cr90,ax ;cr90 rewriting nop nop : nop nop clr1 tmif90 ;interrupt request flag clearing clr1 tmmk90 ;timer interrupt enable set1 tmc90.3 ;timer output inversion enable note wait for more than one cycle of the count clock a fter the instruction rewrit ing cr90 (movw cr90, ax) before clearing the interr upt request flag (tmif90). nop 32 (wait for 64/f x ) note
user?s manual u14801ej3v1ud 97 chapter 7 8-bit timer/event counter 80 7.1 functions of 8-bit timer/event counter 80 8-bit timer/event counter 80 has the following functions. ? interval timer ? external event counter ? square wave output ? pwm output (1) 8-bit interval timer when 8-bit timer/event counter 80 is used as an interval ti mer, it generates an interrupt at a time interval set in advance. table 7-1. interval time of 8-bit timer/event counter 80 minimum interval time maximum interval time resolution at f x = 10.0 mhz operation note at f x = 5.0 mhz operation at f x = 10.0 mhz operation note at f x = 5.0 mhz operation at f x = 10.0 mhz operation note at f x = 5.0 mhz operation 1/f x 100 ns 200 ns 2 8 /f x 25.6 s 51.2 s 1/f x 100 ns 200 ns 2 8 /f x 25.6 s 51.2 s 2 16 /f x 6.55 ms 13.1 ms 2 8 /f x 25.6 s 51.2 s note expanded-specificati on products only. remark f x : system clock oscillation frequency (2) external event counter the number of pulses of an exter nally input signal can be counted. (3) square-wave output a square-wave of arbitrary frequency can be output. table 7-2. square-wave output range of 8-bit timer/event counter 80 minimum pulse width maximum pulse width resolution at f x = 10.0 mhz operation note at f x = 5.0 mhz operation at f x = 10.0 mhz operation note at f x = 5.0 mhz operation at f x = 10.0 mhz operation note at f x = 5.0 mhz operation 1/f x 100 ns 200 ns 2 8 /f x 25.6 s 51.2 s 1/f x 100 ns 200 ns 2 8 /f x 25.6 s 51.2 s 2 16 /f x 6.55 ms 13.1 ms 2 8 /f x 25.6 s 51.2 s note expanded-specificati on products only. remark f x : system clock oscillation frequency (4) pwm output 8-bit resolution pwm output can be produced.
chapter 7 8-bit timer/event counter 80 user?s manual u14801ej3v1ud 98 7.2 configuration of 8- bit timer/event counter 80 8-bit timer/event counter 80 in cludes the following hardware. table 7-3. configuration of 8-bit timer/event counter 80 item configuration timer counter 8 bits 1 (tm80) register compare register: 8 bits 1 (cr80) timer outputs 1 (to80) control registers 8-bit timer mode control register 80 (tmc80) port mode register 2 (pm2) port 2 (p2) figure 7-1. block diagram of 8-bit timer/event counter 80 internal bus internal bus 8-bit compare register 80 (cr80) 8-bit timer counter 80 (tm80) match clear ovf r s inv q q tce80 pwme80 tcl801 tcl800 toe80 ti80/p27/ to80 f x f x /2 8 8-bit timer mode control register 80 (tmc80) p27 output latch to80/p27/ti80 pm27 inttm80 selector (1) 8-bit compare register 80 (cr80) the value specified in cr80 is com pared with the count in 8-bit timer c ounter 80 (tm80). if they match, an interrupt request (inttm80) is issued. cr80 is set with an 8-bit memory manipulation instru ction. any value from 00h to ffh can be set. reset input makes cr80 undefined. cautions 1. before rewriting cr80, stop the timer operation. if cr80 is re written while the timer operation is enabled, the matc h interrupt request signal m ay be generated immediately at the point of rewrite. 2. do not clear cr80 to 00h in pwm output m ode (when pwme80 = 1: bit 6 of 8-bit timer mode control register 80 (tmc80)); othe rwise, pwm output may not be produced normally. (2) 8-bit timer counter 80 (tm80) tm80 is used to count the number of pulses. its contents are read with an 8-bit me mory manipulation instruction. reset input clears tm80 to 00h.
chapter 7 8-bit timer/event counter 80 user?s manual u14801ej3v1ud 99 7.3 8-bit timer/event counter 80 control registers the following three registers are used to control 8-bit timer/event counter 80. 8-bit timer mode control register 80 (tmc80) port mode register 2 (pm2) port 2 (p2) (1) 8-bit timer mode control register 80 (tmc80) tmc80 determines whether to enable or disable 8-bit ti mer counter 80 (tm80), spec ifies the count clock for tm80, and controls the operation of the output controller of 8- bit timer/event counter 80. tmc80 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc80 to 00h. figure 7-2. format of 8-bit timer mode control register 80 tce80 pwme80 0 0 0 tcl801 tcl800 toe80 tmc80 symbol address after reset r/w ff53h 00h r/w <6> <7> 5 4 3 2 1 <0> tcl801 0 0 1 1 8-bit timer counter 80 count clock selection at f x = 10.0 mhz operation note 1 at f x = 5.0 mhz operation tcl800 0 1 0 1 f x f x /2 8 rising edge of ti80 note 2 falling edge of ti80 note 2 tce80 0 1 8-bit timer counter 80 operation control operation disabled (tm80 is cleared to 0.) operation enabled pwme80 0 1 operation mode selection timer counter operation mode pwm output mode toe80 0 1 8-bit timer/event counter output control output disabled (port mode) output enabled 10.0 mhz 39.1 khz 5.0 mhz 19.5 khz notes 1. expanded-specificati on products only. 2. when inputting a clock signal externally, timer output cannot be used. caution always stop the timer before setting tmc80. remark f x : system clock oscillation frequency
chapter 7 8-bit timer/event counter 80 user?s manual u14801ej3v1ud 100 (2) port mode register 2 (pm2) pm2 specifies whether each bit of port 2 is used for input or output. to use the to80/p27/ti80 pin for timer output, t he pm27 and p27 output latch must be reset to 0. to use the to80/p27/ti80 pin for ti mer input, pm27 must be set to 1. pm2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 to ffh. figure 7-3. format of port mode register 2 pm2n 0 1 p2n pin input/output mode selection (n = 0 to 5) output mode (output buffer on) input mode (output buffer off) pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 76 54 symbol address after reset r/w ff22h ffh r/w 3210
chapter 7 8-bit timer/event counter 80 user?s manual u14801ej3v1ud 101 7.4 operation of 8-bit timer/event counter 80 7.4.1 operation as interval timer the interval timer repeatedly generates an in terrupt at a time interval specified by the count value preset in 8-bit compare register 80 (cr80). to operate 8-bit timer/event counter 80 as an interval timer, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter 80 (tm80) (tce80 (bit 7 of 8-bit timer mode control register 80 (tmc80)) = 0). <2> set the count clock of 8-bi t timer/event counter 80 (see table 7-4 ). <3> set a count value in cr80. <4> enable the operation of tm80 (tce80 = 1). when the count value of 8-bit timer counter 80 (tm80) matches the value set in cr80, tm80 is cleared to 0 and continues counting. at the same time, an interrupt request signal (inttm80) is generated. table 7-4 shows the interval time, and figure 7-4 s hows the timing of the interval timer operation. cautions 1. stop the timer operati on before rewriting cr80. if cr 80 is rewritten while the timer operation is enabled, a match si gnal may be generated immediat ely at the point of rewrite (an interrupt request will be generated if in terrupts are enabled). 2. if setting the count clock to tmc80 and en abling the operation of tm80 are performed at the same time with an 8-bit memory manipulation in struction, the error one cycle after the timer has been started may exceed one clock. to use 8-bit timer/even t counter 80 as an interval timer, therefore, make the se ttings in the above sequence. table 7-4. interval time of 8-bit timer/event counter 80 tcl801 tcl800 minimum interval time maximum interval time resolution at f x = 10.0 mhz operation note at f x = 5.0 mhz operation at f x = 10.0 mhz operation note at f x = 5.0 mhz operation at f x = 10.0 mhz operation note at f x = 5.0 mhz operation 0 0 1/f x 100 ns 200 ns 2 8 /f x 25.6 s 51.2 s 1/f x 100 ns 200 ns 0 1 2 8 /f x 25.6 s 51.2 s 2 16 /f x 6.55 ms 13.1 ms 2 8 /f x 25.6 s 51.2 s 1 0 ti80 input cycle 2 8 ti80 input cycle ti80 input edge cycle 1 1 ti80 input cycle 2 8 ti80 input cycle ti80 input edge cycle note expanded-specificati on products only. remark f x : system clock oscillation frequency
chapter 7 8-bit timer/event counter 80 user?s manual u14801ej3v1ud 102 figure 7-4. interval timer operation timing clear clear interrupt acknowledgment interrupt acknowledgment count start interval time interval time interval time count clock tm80 count value cr80 tce80 inttm80 to80 n 01h 00h n 01h 00h n 00h 01h nn nn t remark interval time = (n + 1) t n = 00h to ffh
chapter 7 8-bit timer/event counter 80 user?s manual u14801ej3v1ud 103 7.4.2 operation as external event counter the external event counter counts the number of external clock pulses input to the ti80/p27/ to80 pin by using 8- bit timer counter 80 (tm80). to operate 8-bit timer/event counter 80 as an external event counter, se ttings must be made in the following sequence. <1> set p27 to input mode (pm27 = 1). <2> disable operation of 8-bit timer counter 80 (tm80) (tce80 (bit 7 of 8-bit timer mode control register 80 (tmc80)) = 0). <3> specify the rising or falling edge of ti80 (see table 7-4 ). disable output of to80 (t oe80 (bit 0 of tmc80) = 0) and pwm output (pwme80 (bit 6 of tmc80) = 0). <4> set a count value in cr80. <5> enable the operati on of tm80 (tce80 = 1). each time the valid edge specified by bit 1 (tcl800) of tm c80 is input, the value of 8- bit timer counter 80 (tm80) is incremented. when the count value of tm80 matches the value set in cr80, tm80 is cleared to 0 and continues counting. at the same time, an interrupt request signal (inttm80) is generated. figure 7-5 shows the timing of the external ev ent counter operation (wit h rising edge specified). cautions 1. before rewriting cr80, stop the timer operation. if cr80 is re written while the timer operation is enabled, a match in terrupt request signal may be generated immediately at the point of rewrite. 2. if setting the count clock to tmc80 and en abling the operation of tm80 are performed at the same time with an 8-bit memory manipulation in struction, the error one cycle after the timer has been started may exceed one clock. to use 8-bit timer/ event counter 80 as an external event counter, therefore, make the settings in the above sequence. figure 7-5. external event counter oper ation timing (with rising edge specified) ti80 pin input tm80 count value cr80 tce80 inttm80 00h 01h 02h 03h 04h 05h n ? 1 n 00h 01h 02h 03h n remark n = 00h to ffh
chapter 7 8-bit timer/event counter 80 user?s manual u14801ej3v1ud 104 7.4.3 operation as square-wave output 8-bit timer/event counter 80 can generat e square-wave output of an arbitrary frequency at an interval specified by the count value preset in 8-bi t compare register 80 (cr80). to use 8-bit timer/event counter 80 for square-wave output, settings must be made in the following sequence. <1> set p27 to output mode (pm27 = 0). set the output latch of p27 to 0. <2> disable operation of 8-bit time r counter 80 (tm80) (tce80 = 0). <3> set a count clock for 8-bit timer/event counter 80 (see table 7-5 ), enable output of to80 (toe80 = 1), and disable pwm output (pwme80 = 0). <4> set a count value in cr80. <5> enable the operation of tm80 (tce80 = 1). when the count value of 8-bit timer counter 80 (tm80) matches the value set in cr80, the to80 pin output will be inverted. through application of this mechanism, square waves of any frequen cy can be output. as soon as a match occurs, tm80 is cleared to 0 and continues counti ng, generating an interrupt request signal (inttm80). setting bit 7 (tce80) of tmc80 to 0 clears the square-wave output to 0. table 7-5 shows the square-wave output range, and figure 7-6 shows t he timing of square-wave output. cautions 1. stop the timer operati on before rewriting cr80. if cr 80 is rewritten while the timer operation is enabled, a match in terrupt request signal may be generated immediately at the point of rewrite. 2. if setting the count clock to tmc80 and en abling the operation of tm80 are performed at the same time with an 8-bit memory manipulation in struction, the error one cycle after the timer has been started may exceed one clock. to use 8-bit time r/event counter 80 as a square- wave output, therefore, make the se ttings in the above sequence. table 7-5. square-wave output ra nge of 8-bit timer/event counter tcl801 tcl800 minimum pulse width maximum pulse width resolution at f x = 10.0 mhz operation note at f x = 5.0 mhz operation at f x = 10.0 mhz operation note at f x = 5.0 mhz operation at f x = 10.0 mhz operation note at f x = 5.0 mhz operation 0 0 1/f x 100 ns 200 ns 2 8 /f x 25.6 s 51.2 s 1/f x 100 ns 200 ns 0 1 2 8 /f x 25.6 s 51.2 s 2 16 /f x 6.55 ms 13.1 ms 2 8 /f x 25.6 s 51.2 s note expanded-specificati on products only. remark f x : system clock oscillation frequency
chapter 7 8-bit timer/event counter 80 user?s manual u14801ej3v1ud 105 figure 7-6. square-wave output timing clear clear interrupt acknowledgment interrupt acknowledgment count start count clock tm80 count value cr80 tce80 inttm80 to80 note n 01h 00h n 01h 00h n 00h 01h nn nn note the initial value of to80 is lo w when output is enabled (toe80 = 1).
chapter 7 8-bit timer/event counter 80 user?s manual u14801ej3v1ud 106 7.4.4 operation as pwm output pwm output enables an interrupt to be gener ated repeatedly at an interval specifi ed by the count value preset in 8-bit compare register 80 (cr80). to use 8-bit timer/event counter 80 for pwm output, the following settings are required. <1> set p27 to output mode (pm27 = 0). set the output latch of p27 to 0. <2> disable the operation of 8-bit ti mer counter 80 (tm80) (tce80 = 0). <3> set a count clock for 8-bit timer/event counter (see table 7-4 ), and enable output of to80 (toe80 = 1) and pwm output (pwme80 = 1). <4> set a count value in cr80. <5> enable the operation of tm80 (tce80 = 1). when the count value of 8-bit timer c ounter 80 (tm80) matches the value se t in cr80, tm80 continues counting, and an interrupt request signal (inttm80) is generated. cautions 1. if cr80 is rewritten during timer operation, a high level may be output during the next cycle (see 7.5 (2) setting of 8-bit compare register 80). 2. if setting the count clock to tmc80 and en abling the operation of tm80 are performed at the same time with an 8-bit memory manipulation in struction, the error one cycle after the timer has been started may exceed one clock. to use 8-bit ti mer/event counter 80 as a pwm output, therefore, make the setti ngs in the above sequence. figure 7-7. pwm output timing m m = 01h to ffh count clock 00h 01h ??? m ??? ffh 00h 01h 02h ??? m m + 1 m + 2 ??? ffh 00h 01h ??? m ??? ??? tm80 cr80 ovf tce80 inttm80 to80 note note the initial value of to80 is lo w when output is enabled (toe80 = 1). caution do not set cr80 to 00h in pwm output m ode; otherwise, pwm may not be output normally.
chapter 7 8-bit timer/event counter 80 user?s manual u14801ej3v1ud 107 7.5 notes on using 8-bit timer/event counter 80 (1) error on starting timer an error of up to 1 clock is included in the time between when the timer is st arted and a match signal is generated. this is because 8-bit timer counter 80 (tm 80) is started asynchronously to the count pulse. figure 7-8. start timing of 8-bit timer counter 80 count pulse tm80 count value timer start 00h 01h 02h 03h 04h (2) setting of 8-bit compare register 80 8-bit compare register 80 (cr80) can be set to 00h. therefore, one pulse can be counted when 8-bit timer/event count er 80 operates as an event counter. figure 7-9. external event counter operation timing tl80 input cr80 00h tm80 count value 00h 00h 00h 00h interrupt request flag cautions 1. before rewriting cr 80 in timer counter operation mode (pwme80 (bit 6 of 8-bit timer mode control register 80 (tmc80) = 0), stop the timer operation. if cr80 is rewritten while the timer operation is enabled, a matc h interrupt request si gnal may be generated immediately at the point of rewrite. 2. if cr80 is rewritten during timer opera tion in pwm output operation mode (pwme80 = 1), pulses may not be generated fo r one cycle after the rewrite. 3. do not set cr80 to 00h in pwm operati on mode (when pwme80 = 1) otherwise, pwm may not be output normally.
chapter 7 8-bit timer/event counter 80 user?s manual u14801ej3v1ud 108 (3) timer operation after compare regi ster is rewritten during pwm output when 8-bit compare register 80 (cr80) is rewritten during pwm output, if the new value is smaller than that of 8-bit timer/counter 80 (tm80), a high-level signal may be output for t he next cycle (256 count pulses) after the cr80 value is rewritten. figure 7-10 shows t he timing at which the high-level signal is output. figure 7-10. operation timing after compare register is rewritten during pwm output count clock tm80 cr80 tce80 inttm80 m = 02h to ffh ovf to80 00h 01h m h m ffh 00h 01h 02h ffh 00h 01h 01h cr80 rewritten (4) cautions when stop mode is set be sure to stop timer operations (tce80 = 0) before executing the stop instruction. (5) start timing of external event counter when the rising edge of ti80 is selected as the count clock, start the ti mer when ti80 is low level (tce80 = 0 1). likewise, when the falling edge of ti80 is select ed as the count clock, st art the timer when ti80 is high level (tce80 = 0 1).
user?s manual u14801ej3v1ud 109 chapter 8 watchdog timer 8.1 watchdog timer functions the watchdog timer has the following functions. ? watchdog timer ? interval timer caution select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (wdtm). (1) watchdog timer the watchdog timer is used to detect inadvertent program loops. when an inadvertent loop is detected, a non-maskable interrupt or a reset signal can be generated. table 8-1. inadvertent loop de tection time of watchdog timer inadvertent loop detection time at f x = 10.0 mhz operation note at f x = 5.0 mhz operation 2 11 1/f x 205 s 410 s 2 13 1/f x 819 s 1.64 ms 2 15 1/f x 3.28 ms 6.55 ms 2 17 1/f x 13.1 ms 26.2 ms note expanded-specificati on products only. remark f x : system clock oscillation frequency (2) interval timer the interval timer generates an interrupt at an arbitrary preset interval. table 8-2. interval time interval time at f x = 10.0 mhz operation note at f x = 5.0 mhz operation 2 11 1/f x 205 s 410 s 2 13 1/f x 819 s 1.64 ms 2 15 1/f x 3.28 ms 6.55 ms 2 17 1/f x 13.1 ms 26.2 ms note expanded-specificati on products only. remark f x : system clock oscillation frequency
chapter 8 watchdog timer user?s manual u14801ej3v1ud 110 8.2 watchdog timer configuration the watchdog timer includes the following hardware. table 8-3. configuration of watchdog timer item configuration control registers watchdog timer cl ock selection register (wdcs) watchdog timer mode register (wdtm) figure 8-1. block diagram of watchdog timer internal bus internal bus prescaler selector controller f x 2 6 f x 2 8 f x 2 10 3 7-bit counter clear wdtif wdtmk wdcs2 wdcs1 wdcs0 watchdog timer clock selection register 2 (wdcs) watchdog timer mode register (wdtm) wdtm4 wdtm3 intwdt maskable interrupt request reset intwdt non-maskable interrupt request f x 2 4 run
chapter 8 watchdog timer user?s manual u14801ej3v1ud 111 8.3 watchdog timer control registers the following two registers are us ed to control the watchdog timer. watchdog timer clock selection register (wdcs) watchdog timer mode register (wdtm) (1) watchdog timer clock selection register (wdcs) this register sets the watchdog timer count clock. wdcs is set with an 8-bit memo ry manipulation instruction. reset input clears wdcs to 00h. figure 8-2. format of watchdog ti mer clock selection register wdcs2 0 0 1 1 wdcs1 0 1 0 1 2 4 /f x 2 6 /f x 2 8 /f x 2 10 /f x wdcs0 0 0 0 0 setting prohibited other than above count clock selection at f x = 10.0 mhz operation note at f x = 5.0 mhz operation at f x = 10.0 mhz operation note at f x = 5.0 mhz operation 2 11 /f x 2 13 /f x 2 15 /f x 2 17 /f x interval time 0 0 0 0 0 wdcs2 wdcs1 wdcs0 wdcs 76 54 symbol address after reset r/w ff42h 00h r/w 3210 625 khz 156 khz 39.1 khz 9.77 khz 313 khz 78.1 khz 19.5 khz 4.88 khz 205 s 819 s 3.28 ms 13.1 ms 410 s 1.64 ms 6.55 ms 26.2 ms note expanded-specification products only. remark f x : system clock oscillation frequency
chapter 8 watchdog timer user?s manual u14801ej3v1ud 112 (2) watchdog timer mode register (wdtm) this register sets the operation mode of the watchdog timer, and enables /disables counting of the watchdog timer. wdtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears wdtm to 00h. figure 8-3. format of watc hdog timer mode register run 0 1 watchdog timer operation selection note 1 stop counting. clear counter and start counting. wdtm4 watchdog timer operation mode selection note 2 wdtm3 0 1 1 0 1 1 operation stop interval timer mode (a maskable interrupt is generated upon overflow occurrence) note 3 watchdog timer mode 1 (a non-maskable interrupt is generated upon overflow occurrence) watchdog timer mode 2 (a reset operation is started upon overflow occurrence) 0 0 run 0 0 wdtm4 wdtm3 0 0 0 wdtm <7> 6 5 4 symbol address after reset r/w fff9h 00h r/w 3210 notes 1. once run has been set to 1, it cannot be cleared to 0 by software. ther efore, when counting is started, it cannot be stopped by any means other than reset input. 2. once wdtm3 and wdtm4 have been set to 1, they cannot be cleared to 0 by software. 3. the watchdog timer starts operation as an interval timer when run is set to 1. cautions 1. when the watchdog timer is cleared by setting run to 1, the actual overflow time is up to 0.8% shorter than the time set by the watchdog timer clock selection register (wdcs). 2. to set watchdog timer mode 1 or 2, set wd tm4 to 1 after confirming wdtif (bit 0 of interrupt request flag register 0 (if0)) is set to 0. when watchdog timer mode 1 or 2 is selected with wdtif set to 1, a non-m askable interrupt is generated upon the completion of rewriting wdtm.
chapter 8 watchdog timer user?s manual u14801ej3v1ud 113 8.4 watchdog timer operation 8.4.1 operation as watchdog timer the watchdog timer detects an inadver tent program loop when bit 4 (w dtm4) of the watchdog timer mode register (wdtm) is set to 1. the count clock (inadvertent loop detection time interval) of the watc hdog timer can be selected by bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock selection regi ster (wdcs). by setting bit 7 (run) of wdtm to 1, the watchdog timer is started. set run to 1 within the set inadvertent loop det ection time interval after the watchdog timer has been started. by setting run to 1, the watchdog timer can be cleared and start counting. if run is not set to 1, and the inadvertent l oop detection time is exceeded, a system rese t signal or a non-maskable interrupt is generated, depending on the value of bit 3 (wdtm3) of wdtm. the watchdog timer continues operation in halt mode, but stops in stop mode. therefore, first set run to 1 to clear the watchdog timer before exec uting the stop instruction. caution the actual inadvertent loop detection time may be up to 0. 8% shorter than the set time. table 8-4. inadvertent loop det ection time of watchdog timer wdcs2 wdcs1 wdcs0 inadvertent loop detection time at f x = 10.0 mhz operation note at f x = 5.0 mhz operation 0 0 0 2 11 1/f x 205 s 410 s 0 1 0 2 13 1/f x 819 s 1.64 ms 1 0 0 2 15 1/f x 3.28 ms 6.55 ms 1 1 0 2 17 1/f x 13.1 ms 26.2 ms note expanded-specificati on products only. remark f x : system clock oscillation frequency
chapter 8 watchdog timer user?s manual u14801ej3v1ud 114 8.4.2 operation as interval timer when bits 4 and 3 (wdtm4, wdtm3) of the watchdog timer mode register (wdtm) are set to 0 and 1, respectively, the watchdog timer operates as an interval ti mer that repeatedly generates an interrupt at an interval specified by a preset count value. select a count clock (or interval time) by setting bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock selection register (wdcs). the watc hdog timer starts operation as an interv al timer when the run bit (bit 7 of wdtm) is set to 1. in interval timer mode, the interrupt mask flag (wdt mk) is valid, and a maskable interrupt (intwdt) can be generated. the priority of intwdt is set as the highest of all the maskable interrupts. the interval timer continues operation in halt mode, but stops in stop mode. therefore, first set run to 1 to clear the interval timer before ex ecuting the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (when watchdog timer mode is selected), interval timer mode is not set unless a reset signal is input. 2. the interval time may be up to 0.8% shorter than the set time when wdtm has just been set. table 8-5. interval gene rated using interval timer wdcs2 wdcs1 wdcs0 interval time at f x = 10.0 mhz operation note at f x = 5.0 mhz operation 0 0 0 2 11 1/f x 205 s 410 s 0 1 0 2 13 1/f x 819 s 1.64 ms 1 0 0 2 15 1/f x 3.28 ms 6.55 ms 1 1 0 2 17 1/f x 13.1 ms 26.2 ms note expanded-specificati on products only. remark f x : system clock oscillation frequency
user?s manual u14801ej3v1ud 115 chapter 9 serial interface 20 9.1 functions of serial interface 20 serial interface 20 has the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not performed. power consumption is minimized in this mode. (2) asynchronous serial interface (uart) mode this mode is used to send and receive the one byte of data that follows a start bit. it supports full-duplex communication. serial interface 20 contains a uart-dedicated baud rate generator, enabling communication over a wide range of baud rates. it is also possible to define baud ra tes by dividing the frequency of the clock input to the asck20 pin. (3) 3-wire serial i/o mode (swit chable between msb-first a nd lsb-first transmission) this mode is used to transmit 8-bit data, using three lines: a serial clock (sck20) line and two serial data lines (si20 and so20). as it supports simultaneous transmissi on and reception, 3-wire serial i/o mode requires less processing time for data transmission than asynchr onous serial interface mode. because, in 3-wire serial i/o mode, it is possible to select whether 8-bit dat a transmission begins with the msb or lsb, serial interface 20 can be connected to any device regardless of whether that device is designed for msb-first or lsb-first transmission. 3-wire serial i/o mode is useful for connecting peri pheral i/o circuits and display controllers having conventional synchronous serial interfaces, such as those of the 75x/xl, 78k, and 17k series devices. 9.2 configuration of serial interface 20 serial interface 20 includes the following hardware. table 9-1. configuration of serial interface 20 item configuration registers transmission shi ft register 20 (txs20) reception shift register 20 (rxs20) receive buffer register 20 (rxb20) control registers serial operati on mode register 20 (csim20) asynchronous serial interfac e mode register 20 (asim20) asynchronous serial interface st atus register 20 (asis20) baud rate generator control register 20 (brgc20) port mode register 2 (pm2) port 2 (p2)
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 116 internal bus receive buffer register 20 (rxb20) switching of the first bit asynchronous serial interface status register 20 (asis20) serial operation mode register 20 (csim20) receive shift register 20 (rxs20) csie20 sse20 dap20 dir20 csck20 ckp20 pe20 fe20 ove20 txe20 rxe20 ps201 ps200 cl20 sl20 asynchronous serial interface mode register 20 (asim20) transmit shift register 20 (txs20) transmit shift clock selector csie20 dap20 data phase control receive shift clock si20/p22/ rxd20 so20/p21/ txd20 4 parity detection stop bit detection receive data counter parity operation stop bit addition transmit data counter sl20, cl20, ps200, ps201 reception enabled receive clock detection clock start bit detection csie20 csck20 sck20/p20/ asck20 ss20/p23 clock phase control reception detected internal clock output external clock input transmit and receive clock control baud rate generator note 4 tps203 tps202 tps201 tps200 csie20 csck20 f x /2 to f x /2 8 baud rate generator control register 20 (brgc20) intst20 intsr20/intcsi20 internal bus figure 9-1. block diagram of serial interface 20 note see figure 9-2 for the configuration of the baud rate generator. port mode register (pm21)
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 117 reception detection clock transmit shift clock receive shift clock reception detected txe20 rxe20 csie20 selector selector selector 1/2 1/2 transmit clock counter (3 bits) receive clock counter (3 bits) 4 f x /2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 2 asck20/sck20/p20 tps203 tps202 tps201 tps200 baud rate generator control register 20 (brgc20) internal bus figure 9-2. block diagram of baud rate generator 20
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 118 (1) transmit shift register 20 (txs20) txs20 is a register in which transmi t data is prepared. the transmit data is output from txs20 bit-serially. when the data length is seven bits, bits 0 to 6 of t he data in txs20 will be transmi t data. writing data to txs20 triggers transmission. txs20 can be written with an 8-bit memory m anipulation instruction, but cannot be read. reset input sets txs20 to ffh. caution do not write to txs20 during transmission. txs20 and receive buffer register 20 (rxb20) are mapped at the same address, so that any attempt to read from txs20 results in a value being read from rxb20. (2) receive shift register 20 (rxs20) rxs20 is a register in which serial data, received at the rxd 20 pin, is converted to parallel data. once one entire byte has been received, rxs20 feeds the rece ive data to receive buffer register 20 (rxb20). rxs20 cannot be manipulated di rectly by a program. (3) receive buffer register 20 (rxb20) rxb20 holds a receive data. new receive data is transfe rred from receive shift register 20 (rxs20) at every 1-byte data reception. when the data length is seven bits, the receive data is sent to bits 0 to 6 of rxb20, in which the msb is always fixed to 0. rxb20 can be read with an 8-bit memory manipul ation instruction, but cannot be written. reset input makes rxb20 undefined. caution rxb20 and transmit shift register 20 (txs 20) are mapped at the sam e address, so that any attempt to write to rxb20 results in a value being written to txs20. (4) transmission controller the transmission controller controls transmission. for ex ample, it adds start, parity, and stop bits to the data in transmit shift register 20 (txs20), according to the setting of asynchronous serial interface mode register 20 (asim20). (5) reception controller the reception controller controls re ception according to the setting of asynchronous serial interface mode register 20 (asim20). it also checks for errors, such as parity errors, during recepti on. if an error is detected, asynchronous serial interface status register 20 (asis20) is set accord ing to the status of the error.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 119 9.3 control registers of serial interface 20 serial interface 20 is controlled by the following six registers. ? serial operation mode register 20 (csim20) ? asynchronous serial interfac e mode register 20 (asim20) ? asynchronous serial interface status register 20 (asis20) ? baud rate generator contro l register 20 (brgc20) ? port mode register 2 (pm2) ? port 2 (p2) (1) serial operation mode register 20 (csim20) csim20 is set when serial interface 20 is used in 3-wire serial i/o mode. csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. figure 9-3. format of serial operation mode register 20 csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection outputs at the falling edge of sck20. outputs at the rising edge of sck20. ss20 pin selection function of ss20/p23 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is active low, and sck20 is at high level in the idle state. clock is active high, and sck20 is at low level in the idle state. cautions 1. bits 4 and 5 must both be set to 0. 2. csim20 must be cleared to 00h, if uart mode is selected.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 120 (2) asynchronous serial interface mode register 20 (asim20) asim20 is set when serial interface 20 is us ed in asynchronous serial interface mode. asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. figure 9-4. format of asynchronous serial interface mode register 20 txe20 0 1 transmit operation control txe20 rxe20 ps201 ps200 cl20 sl20 00 asim20 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stop transmit operation enable rxe20 0 1 receive operation control receive operation stop receive operation enable ps201 0 0 1 1 parity bit specification ps200 0 1 0 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error occurs). odd parity even parity cl20 0 1 transmit data character length specification 7 bits 8 bits sl20 0 1 transmit data stop bit length 1 bit 2 bits cautions 1. bits 0 and 1 must both be set to 0. 2. if 3-wire serial i/o mode is select ed, asim20 must be cleared to 00h. 3. switch operating modes after halt ing the serial transmit/receive operation.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 121 table 9-2. operating mode settings of serial interface 20 (1) operation stop mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p22 pm21 p21 pm20 p20 first bit shift clock p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/sck20/ asck20 pin function 0 0 0 note 1 note 1 note 1 note 1 note 1 note 1 ? ? p22 p21 p20 other than above setting prohibited (2) 3-wire serial i/o mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p22 pm21 p21 pm20 p20 first bit shift clock p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/sck20/ asck20 pin function 0 1 external clock sck20 input 1 0 1 0 1 msb internal clock sck20 output 0 1 external clock sck20 input 0 0 1 1 1 1 note 2 note 2 0 1 0 1 lsb internal clock si20 note 2 so20 (cmos output) sck20 output other than above setting prohibited (3) asynchronous serial interface mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p22 pm21 p21 pm20 p20 first bit shift clock p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/sck20/ asck20 pin function 1 external clock asck20 input 1 0 0 0 0 note 1 note 1 0 1 note 1 note 1 internal clock p22 txd20 (cmos output) p20 1 external clock asck20 input 0 1 0 0 0 1 note 1 note 1 note 1 note 1 internal clock p21 p20 1 external clock asck20 input 1 1 0 0 0 1 0 1 note 1 note 1 lsb internal clock rxd20 txd20 (cmos output) p20 other than above setting prohibited notes 1. these pins can be used for port functions. 2. when only transmission is used, this pin can be used as p22 (cmos i/o). remark : don't care.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 122 (3) asynchronous serial interface status register 20 (asis20) asis20 indicates the type of a recepti on error, if it occurs while asynch ronous serial interface mode is set. asis20 is read with a 1-bit or 8-bit memory manipulation instruction. the contents of asis 20 are undefined in 3-wire serial i/o mode. reset input clears asis20 to 00h. figure 9-5. format of asynchronous se rial interface status register 20 pe20 0 1 parity error flag 00000 pe20 fe20 ove20 asis20 symbol address after reset r/w ff71h 00h r 76543210 no parity error occurred. a parity error occurred (when the transmit parity and receive parity did not match). fe20 0 1 flaming error flag no framing error occurred. a framing error occurred (no stop bit detected). note 1 ove20 0 1 overrun error flag no overrun error occurred. an overrun error occurred note 2 . (the subsequent receive operation was completed before data was read from the receive buffer register.) notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asim 20), the stop bit detection at rec eption is performed with 1 bit. 2. be sure to read receive buffer register 20 (r xb20) when an overrun error occurs. if not, every time the data is received an overrun error is generated.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 123 (4) baud rate generator cont rol register 20 (brgc20) brgc20 is used to specify the serial clock for serial interface 20. brgc20 is set with an 8-bit memo ry manipulation instruction. reset input clears brgc20 to 00h. figure 9-6. format of baud rate generator control register 20 tps203 0 0 0 0 0 0 0 0 1 selection of source clock for baud rate generator at f x = 10.0 mhz operation note at f x = 5.0 mhz operation tps203 tps202 tps201 tps200 0000 brgc20 symbol address after reset r/w ff73h 00h r/w 76543210 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 external clock input to the asck20 pin note 2 setting prohibited other than above tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 5.0 mhz 2.5 mhz 1.25 mhz 625 khz 313 khz 156 khz 78.1 khz 39.1 khz 2.5 mhz 1.25 mhz 625 khz 313 khz 156 khz 78.1 khz 39.1 khz 19.5 khz notes 1. expanded-specificati on products only. 2. an external clock can be used only in uart mode. cautions 1. when writing to brgc20 is perfo rmed during a communication operation, the output of the baud rate generator is disrupted and communication cannot be performed normally. be sure not to write to brgc20 during a communication operation. 2. be sure not to select n = 1 during operation at f x > 2.5 mhz in uart mode because the resulting baud rate exceeds the rated range. 3. be sure not to select n = 2 during opera tion at fx > 5.0 mhz in uart mode because the resulting serial clock exceeds the rated range. 4. be sure not to select n = 1 during opera tion at fx > 5.0 mhz in 3-wire serial i/o mode because the resulting serial clock exceeds the rated range. 5. when the external input clock is selected, set port mode register 2 (pm2) to input mode. remarks 1. f x : system clock oscillation frequency 2. n: value determined by setting tps200 through tps203 (1 n 8)
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 124 the baud rate transmit/receive clock to be generated is either a signal generated by dividing the system clock, or a signal generated by dividing the clock input from the asck20 pin. (a) generation of baud ra te transmit/receive clo ck from system clock the transmit/receive clock is generated by dividi ng the system clock. the baud rate of a clock generated from the system clock is estima ted by using the following expression. [baud rate] = [bps] f x : system clock oscillation frequency n: value determined by settings of tps200 through tps203 as shown in figure 9-6 (2 n 8) table 9-3. example of relationship between system clock and baud rate f x = 10.0 mhz note f x = 5.0 mhz f x = 4.9152 mhz baud rate (bps) n brgc20 set value error (%) n brgc20 set value error (%) n brgc20 set value error (%) 1,200 ? ? 1.73 8 70h 1.73 8 70h 0 2,400 8 70h 7 60h 7 60h 4,800 7 60h 6 50h 6 50h 9,600 6 50h 5 40h 5 40h 19,200 5 40h 4 30h 4 30h 38,400 4 30h 3 20h 3 20h 76,800 3 20h 2 10h 2 10h note expanded-specificati on products only. cautions 1. be sure not to select n = 1 during opera tion at fx > 2.5 mhz because the resulting baud rate exceeds the rated range. 2. be sure not to select n = 2 during operation at fx > 5.0 mhz because the resulting baud rate exceeds the rated range. f x 2 n + 1 8
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 125 (b) generation of baud rate tr ansmit/receive clock from externa l clock input from asck20 pin the transmit/receive clock is generated by dividing t he clock input from the asck20 pin. the baud rate of a clock generated from the clock input from t he asck20 pin is estimated by using the following expression. [baud rate] = [bps] f asck : frequency of clock input from the asck20 pin table 9-4. relationship between asck20 pin input frequency and baud rate (when brg c20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 (c) generation of serial clock in 3- wire serial i/o mode from system clock the serial clock is generated by di viding the system clock. the seri al clock frequency is estimated by using the following expression. brgc20 does not need to be set when an external serial clock is input to the sck20 pin. serial clock frequency = [hz] f x : system clock oscillation frequency n: value (shown in figure 9-6) dete rmined by setting tps200 through tps203 (1 n 8) f asck 16 f x 2 n+1
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 126 9.4 operation of serial interface 20 serial interface 20 provides the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode 9.4.1 operation stop mode in operation stop mode, serial transfer is not executed; theref ore, the power consumpt ion can be reduced. the p20/sck20/asck20, p21/so20/tx d20, and p22/si20/rxd20 pins can be used as normal i/o ports. (1) register setting operation stop mode is set by serial operation mode register 20 (csim20) and asynchronous serial interface mode register 20 (asim20). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. csie20 0 1 3-wire serial i/o mode operation control operation disabled operation enabled csie20 sse20 0 0 dap20 dir20 csck20 ckp20 csim20 <7> 6 5 4 symbol address after reset r/w ff72h 00h r/w 3210 caution bits 4 and 5 must both be set to 0. (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. txe20 0 1 transmit operation control transmit operation stop transmit operation enable receive operation stop receive operation enable rxe20 0 1 receive operation control txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 caution bits 0 and 1 must both be set to 0.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 127 9.4.2 asynchronous serial interface (uart) mode in this mode, the one-byte data followi ng the start bit is transmitted/receiv ed and thus full-duplex communication is possible. this device incorporates a uart- dedicated baud rate generator that enabl es communication at the desired baud rate from many options. in addition, the baud rate can also be defined by dividing the clock input to the asck20 pin. the uart-dedicated baud rate generator can also output t he 31.25 kbps baud rate that complies with the midi standard. (1) register setting uart mode is set by serial operat ion mode register 20 (csim20), a synchronous serial interface mode register 20 (asim20), asynchronous serial interface st atus register 20 (asis20) , baud rate generator control register 20 (brgc20), port mode r egister 2 (pm2), and port 2 (p2).
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 128 (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. set csim20 to 00h when uart mode is selected. csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection outputs at the falling edge of sck20. outputs at the rising edge of sck20. ss20 pin selection function of ss20/p23 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is active low, and sck20 is high level in the idle state. clock is active high, and sck20 is low level in the idle state. caution bits 4 and 5 must both be set to 0.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 129 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. txe20 0 1 transmit operation control transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission. parity check is not performed at reception. (no parity error is generated.) odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 cautions 1. bits 0 and 1 must both be set to 0. 2. switch operating modes after halt ing the serial transmit/receive operation.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 130 (c) asynchronous serial interface status register 20 (asis20) asis20 is read with a 1-bit or 8-bit memory manipulation instruction. reset input clears asis20 to 00h. pe20 0 1 parity error flag parity error did not occur parity error occurred (when the parity of transmit data did not match) framing error did not occur framing error occurred (when stop bit was not detected) note 1 overrun error did not occur overrun error occurred note 2 (when the next receive operation was completed before the data was read from the receive buffer register) fe20 0 1 0 1 flaming error flag overrun error flag ove20 0 0 0 0 0 pe20 fe20 ove20 asis20 76 54 symbol address after reset r/w ff71h 00h r 3210 notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asi m20), the stop bit detection at reception is performed with 1 bit. 2. be sure to read receive buffer register 20 (rxb20) when an overrun error occurs. if not, every time the data is receiv ed an overrun error is generated.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 131 (d) baud rate generator cont rol register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input clears brgc20 to 00h. tps203 0 0 0 0 0 0 0 0 1 tps202 0 0 0 0 1 1 1 1 0 tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 selection of source clock for baud rate generator at f x = 10.0 mhz operation note at f x = 5.0 mhz operation other than above tps203 tps202 tps201 tps200 0 0 0 0 brgc20 76 54 symbol address after reset r/w ff73h 00h r/w 3210 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 external clock input to asck20 pin setting prohibited 5.0 mhz 2.5 mhz 1.25 mhz 625 khz 313 khz 156 khz 78.1 khz 39.1 khz 2.5 mhz 1.25 mhz 625 khz 313 khz 156 khz 78.1 khz 39.1 khz 19.5 khz note expanded-specificati on products only. cautions 1. when writing to brgc20 is performed during a communication operation, the output of the baud rate generator is disrupted and communication cannot be performed normally. be sure not to write to brgc20 during a communication operation. 2. be sure not to select n = 1 during operation at f x > 2.5 mhz because the resulting baud rate exceeds the rated range. 3. be sure not to select n = 2 during ope ration at fx > 5.0 mhz because the resulting baud rate exceeds the rated range. 4. when the external input clock is selected, set port mode register 2 (pm2) to input mode. remarks 1. f x : system clock oscillation frequency 2. n: value determined by setting tps200 through tps203 (1 n 8) the baud rate transmit/receive clock to be generated is either a signal divided from the system clock, or a signal divided from the clock input from the asck20 pin. (i) generation of baud rate transm it/receive clock from system clock the transmit/receive clock is generated by dividing the system clock. the baud rate of the clock generated from the system clock is estimat ed by using the following expression. [baud rate] = [bps] f x : system clock oscillation frequency n: value determined by setting tps200 through tps203 as shown in the above table (2 n 8) f x 2 n + 1 8
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 132 table 9-5. example of relationship between system clock and baud rate f x = 10.0 mhz note f x = 5.0 mhz f x = 4.9152 mhz baud rate (bps) n brgc20 set value error (%) n brgc20 set value error (%) n brgc20 set value error (%) 1,200 ? ? 1.73 8 70h 1.73 8 70h 0 2,400 8 70h 7 60h 7 60h 4,800 7 60h 6 50h 6 50h 9,600 6 50h 5 40h 5 40h 19,200 5 40h 4 30h 4 30h 38,400 4 30h 3 20h 3 20h 76,800 3 20h 2 10h 2 10h note expanded-specificati on products only. cautions 1. be sure not to select n = 1 during opera tion at fx > 2.5 mhz because the resulting baud rate exceeds the rated range. 2. be sure not to select n = 2 during operation at fx > 5.0 mhz because the resulting baud rate exceeds the rated range. (ii) generation of baud rate tr ansmit/receive clock from external clock input from asck20 pin the transmit/receive clock is generated by dividing the clock input from t he asck20 pin. the baud rate of the clock generated from the clock input from the asck20 pin is estimated by using the following expression. [baud rate] = [bps] f asck : frequency of clock input from the asck20 pin table 9-6. relationship between asck20 pin input frequency and baud rate (when brg c20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 f asck 16
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 133 (2) communication operation (a) data format the transmit/receive data format is as shown in figur e 9-7. one data frame c onsists of a start bit, character bits, a parity bit, and stop bit(s). the specification of the c haracter bit length in one data frame, parit y selection, and spec ification of the stop bit length is carried out with asynchronous serial interface mode register 20 (asim20). figure 9-7. format of asynchronous serial interface transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit start bit one data frame ? start bits ................... 1 bit ? character bits............ 7 bits/8 bits ? parity bits .................. ev en parity/odd parity/ 0 parity/no parity ? stop bit(s).................. 1 bit/2 bits when 7 bits is selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (b it 7) is ignored, and in reception t he most significant bit (bit 7) is always "0". the serial transfer rate is selected by baud rate generator control register 20 (brgc20). if a serial data receive error is generated, the re ceive error contents can be determined by reading the status of asynchronous serial inte rface status register 20 (asis20).
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 134 (b) parity types and operation the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmitting side and the receivi ng side. with even parit y and odd parity, a one-bit (odd number) error can be detected. with 0 par ity and no parity, an erro r cannot be detected. (i) even parity ? at transmission the parity bit is determined so t hat the number of bits with a va lue of "1" in the transmit data including the parity bit is even. the parity bit value should be as follows. the number of bits with a value of "1 " is an odd number in transmit data: 1 the number of bits with a value of "1 " is an even number in transmit data: 0 ? at reception the number of bits with a value of "1" in the receive data including the parity bit is counted, and if the number is odd, a parity error occurs. (ii) odd parity ? at transmission conversely to even parity, the parit y bit is determined so that the num ber of bits with a value of "1" in the transmit data including the parity bit is odd. the parity bit value should be as follows. the number of bits with a value of "1 " is an odd number in transmit data: 0 the number of bits with a value of "1 " is an even number in transmit data: 1 ? at reception the number of bits with a value of "1" in the receive data including the parity bit is counted, and if the number is even, a parity error occurs. (iii) 0 parity when transmitting, the parity bit is set to "0" irrespective of the transmit data. at reception, a parity bit check is not perform ed. therefore, a parit y error does not occur, irrespective of whether the parity bit is set to "0" or "1". (iv) no parity a parity bit is not added to the transmit data. at reception, data is received a ssuming that there is no parity bit. since there is no parity bit, a parity error does not occur.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 135 (c) transmission a transmit operation is started by wr iting transmit data to transmit shi ft register 20 (txs20). the start bit, parity bit, and stop bit(s) are added automatically. when the transmit operation starts, the data in txs20 is shifted out, and when txs20 is empty, a transmission completion interr upt (intst20) is generated. figure 9-8. asynchronous serial interf ace transmission completion interrupt timing (a) stop bit length: 1 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 (b) stop bit length: 2 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 caution do not rewrite asynchronous serial in terface mode register 20 (asim20) during a transmit operation. if the asim20 regi ster is rewritten during transmission, subsequent transmission may not be perf ormed (the normal state is restored by reset input). it is possible to determine whether transm ission is in progress by software by using a transmission completion interrupt (intst20) or the interrupt request flag (stif20) set by intst20.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 136 (d) reception when bit 6 (rxe20) of asynchronous serial interface mode register 20 (asim20) is set to 1, a receive operation is enabled and sampling of t he rxd20 pin input is performed. rxd20 pin input sampling is performed using t he serial clock specified by brgc20. when the rxd20 pin input becomes lo w, the 3-bit counter starts count ing, and at the time when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output. if the rxd20 pin input sampled again as a result of this st art timing signal is low, it is identified as a start bit, the 3-bit counter is initializ ed and starts counting, and data sampli ng is performed. when character data, a parity bit, and one stop bit ar e detected after the start bit, re ception of one frame of data ends. when one frame of data has been received, the receive data in the shift r egister is transferred to receive buffer register 20 (rxb20), and a reception co mpletion interrupt (intsr20) is generated. if an error occurs, the receive data in which the error occurred is still transferred to rxb20, and intsr20 is generated. if the rxe20 bit is reset to 0 during the receive oper ation, the receive operati on is stopped immediately. in this case, the contents of rxb20 and asynchronous serial interface status register 20 (asis20) are not changed, and intsr 20 is not generated. figure 9-9. asynchronous serial inte rface reception completion interrupt timing stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 caution be sure to read recei ve buffer register 20 (rxb20) even if a receive error occurs. if rxb20 is not read, an overrun error will occu r when the next data is received, and the receive error state will continue indefinitely.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 137 (e) receive errors the following three errors may occur during a receive operation: a parity error, a framing error, and an overrun error. after data reception, an error flag is se t in asynchronous serial interface status register 20 (asis20). receive error caus es are shown in table 9-7. it is possible to determine what kind of error o ccurred during reception by reading the contents of asis20 in the reception error interrupt servicing (see table 9-7 and figure 9-10 ). the contents of asis20 are reset to 0 by reading receive buffer regist er 20 (rxb20) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). table 9-7. receive error causes receive errors cause parity error transmission-time parity and reception data parity do not match. framing error stop bit not detected overrun error reception of next data is completed before data is read from receive buffer register. figure 9-10. receive error timing (a) parity error occurred stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 (b) framing error or overrun error occurred stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 cautions 1. the contents of the asis20 register are reset to 0 by readi ng receive buffer register 20 (rxb20) or receiving the next data. to ascertain the error contents, read asis20 before reading rxb20. 2. be sure to read receive buffer register 20 (rxb20) even if a receive error occurs. if rxb20 is not read, an overrun error will o ccur when the next data is received, and the receive error state will continue indefinitely.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 138 (f) reading receive data when the reception completion inte rrupt (intsr20) is generated, r ead the value of receive buffer register 20 (rxb20) to read the receive data. when reading the receive data stored in receive buffer register 20 (rxb20), enable the receive operation (rxe20 = 1). remark if the receive data must be read after the receive operation has been disabled (rxe20 = 0), use either method below. (a) after waiting for 1 cycle or more of the s ource clock selected by brgc20, set rxe20 to 0, and then read t he receive data. (b) set bit 2 (dir20) of serial operation mode r egister 20 (csim20) to 1, and read the receive data. example program for (a) (brgc29 = 00h (source clock = fx/2)) intrxe: ; reception completion interrupt routine nop ; 2 clocks clr1 rxe20 ; stop reception operation mov a,rxb20 ; read receive data example program for (b) intrxe: ; reception completion interrupt routine set1 csim20.2 ; set the dir20 flag to lsb first clr1 rxe20 ; stop reception operation mov a,rxb20 ; read receive data
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 139 (3) cautions rela ted to uart mode (a) when bit 7 (txe20) of asynchronous serial inte rface mode register 20 ( asim20) is cleared during transmission, be sure to set transmit shift regist er 20 (txs20) to ffh, then set txe20 to 1 before executing the next transmission. (b) when bit 6 (rxe20) of asynchronous serial inte rface mode register 20 ( asim20) is cleared during reception, receive buffer register 20 (rxb20) and t he receive completion interrupt (intsr20) are as follows. parity rxd20 pin rxb20 intsr20 <3> <1> <2> when rxe20 is set to 0 at the time indicated by <1> , rxb20 holds the previous data and intsr20 is not generated. when rxe20 is set to 0 at the time indicated by <2> , rxb20 renews the data and intsr20 is not generated. when rxe20 is set to 0 at the time indicated by <3> , rxb20 renews the data and intsr20 is generated.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 140 9.4.3 3-wire serial i/o mode the 3-wire serial i/o mode is useful fo r connection of peripheral i/os and display controllers, etc., that incorporate a conventional synchronous serial interface, such as the 75xl series, 78k series, 17k series, etc. communication is performed using three lines: the serial clock (sck20), serial output (so20), and serial input (si20). (1) register setting 3-wire serial i/o mode settings are performed usi ng serial operation mode register 20 (csim20), asynchronous serial interface mode register 20 (asim 20), baud rate generator contro l register 20 (brgc20), port mode register 2 (pm2), and port 2 (p2). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection outputs at the falling edge of sck20. outputs at the rising edge of sck20. ss20 pin selection function of ss20/p23 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is active low, and sck20 is at high level in the idle state. clock is active high, and sck20 is at low level in the idle state. caution bits 4 and 5 must both be set to 0.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 141 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. when 3-wire serial i/o mode is selected, asim20 must be set to 00h. txe20 0 1 transmit operation control transmit operation stop transmit operation enable receive operation stop receive operation enable rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission. parity check is not performed at reception. (no parity error occurs.) odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 character length specification 7 bits 8 bits 1 bit 2 bits transmit data sop bit length specification txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 cautions 1. bits 0 and 1 must both be set to 0. 2. switch operating modes after halt ing the serial transmit/receive operation.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 142 (c) baud rate generator cont rol register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input clears brgc20 to 00h. tps203 0 0 0 0 0 0 0 0 tps202 0 0 0 0 1 1 1 1 tps201 0 0 1 1 0 0 1 1 tps200 0 1 0 1 0 1 0 1 n 1 2 3 4 5 6 7 8 selection of source clock for baud rate generator other than above tps203 tps202 tps201 tps200 0 0 0 0 brgc20 76 54 symbol address after reset r/w ff73h 00h r/w 3210 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 setting prohibited 5.0 mhz 2.5 mhz 1.25 mhz 625 khz 313 khz 156 khz 78.1 khz 39.1 khz 2.5 mhz 1.25 mhz 625 khz 313 khz 156 khz 78.1 khz 39.1 khz 19.5 khz at f x = 10.0 mhz operation note at f x = 5.0 mhz operation note expanded-specificati on products only. cautions 1. when writing to brgc20 is pe rformed during a communication operation, the baud rate generator output is disrupted and communication cannot be performed normally. be sure not to write to brgc20 during a communication operation. 2. be sure not to select n = 1 during operation at f x > 5.0 mhz in 3-wire serial i/o mode because the resulting serial clock exceeds the rated range. 3. when the external input clock is selected, set port mode register 2 (pm2) to input mode. remarks 1. f x : system clock oscillation frequency 2. n: value determined by setting tps200 through tps203 (1 n 8) if the internal clock is used as the serial clock fo r 3-wire serial i/o mode, set bits tps200 to tps203 to set the frequency of the serial clock. to obtain the frequency to be set, use the following expression. when an external serial clock is used, setting brgc20 is not necessary. serial clock frequency = [hz] f x : system clock oscillation frequency n: value determined by setting tps200 to tps203 as shown in the above table (1 n 8) f x 2 n + 1
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 143 (2) communication operation in 3-wire serial i/o mode, data transmission/recept ion is performed in 8-bit units. data is transmitted/received bit by bit in syn chronization with the serial clock. transmit shift register 20 (txs20/sio20) and receiv e shift register 20 (rxs20) shift operations are performed in synchronization with the fall of the serial clock (sck20). then transmit data is held in the so20 latch and output from the so 20 pin. also, receive data input to t he si20 pin is latched in receive buffer register 20 (rxb20/sio20) on the rise of sck20. at the end of an 8-bit transfer, the operation of txs20/ sio20 and rxs20 stops automatically, and the interrupt request signal (i ntcsi20) is generated. figure 9-11. 3-wire serial i/o mode timing (1/7) (i) master operation timing (when dap20 = 0, ckp20 = 0, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 note si20 sio20 write intcsi20 note the value of the last bit previously output is output.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 144 figure 9-11. 3-wire serial i/o mode timing (2/7) (ii) slave operation timing (when dap20 = 0, ckp20 = 0, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 note so20 sio20 write intcsi20 note the value of the last bit previously output is output. (iii) slave operation (when dap20 = 0, ckp20 = 0, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 note 1 do6 do5 do4 do3 do2 do1 do0 note 2 sck20 si20 so20 hi-z hi-z ss20 sio20 write intcsi20 notes 1. the value of the last bit previously output is output. 2. do0 is output until ss20 rises. when ss20 is high, so20 is in a high-impedance state.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 145 figure 9-11. 3-wire serial i/o mode timing (3/7) (iv) master operation (when dap20 = 0, ckp20 = 1, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 si20 sio20 write intcsi20 (v) slave operation (when dap20 = 0, ckp20 = 1, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 so20 sio20 write intcsi20 sio20 write (master) note note the data of si20 is loaded at the first rising edge of sck20. ma ke sure that the master outputs the first bit before the first rising of sck20.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 146 figure 9-11. 3-wire serial i/o mode timing (4/7) (vi) slave operation (when dap20 = 0, ckp20 = 1, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 note 2 sck20 si20 hi-z hi-z so20 sio20 write ss20 intcsi20 do0 sio20 write (master) note 1 notes 1. the data of si20 is loaded at the first rising edge of sck20. make sure that the master outputs the first bit before the first rising of sck20. 2. so20 is high until ss20 rises after completion of do0 output. when ss20 is high, so20 is in a high-impedance state. (vii) master operation (when dap20 = 1, ckp20 = 0, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 si20 sio20 write intcsi20
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 147 figure 9-11. 3-wire serial i/o mode timing (5/7) (viii) slave operation (when dap20 = 1, ckp20 = 0, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 so20 sio20 write intcsi20 sio20 write (master) note note the data of si20 is loaded at the first falling edge of sck20. ma ke sure that the master outputs the first bit before the first falling of sck20. (ix) slave operation (when dap20 = 1, ckp20 = 0, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 note 2 sck20 si20 hi-z hi-z so20 sio20 write ss20 intcsi20 do0 sio20 write (master) note 1 notes 1. the data of si20 is loaded at the first falling edge of sck20. make sure that the master outputs the first bit before the first falling of sck20. 2. so20 is high until ss20 rises after completion of do0 output. when ss20 is high, so20 is in a high-impedance state.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 148 figure 9-11. 3-wire serial i/o mode timing (6/7) (x) master operation (when dap20 = 1, ckp20 = 1, sse20 = 0) 12345678 do7 note do6 do5 do4 do3 do2 do1 di7 di6 di5 di4 di3 di2 di1 sck20 so20 si20 sio20 write intcsi20 di0 do0 note the value of the last bit previously output is output. (xi) slave operation (when dap20 = 1, ckp20 = 1, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 sck20 si20 so20 sio20 write intcsi20 do7 note do6 do5 do4 do3 do2 do1 do0 di0 note the value of the last bit previously output is output.
chapter 9 serial interface 20 user?s manual u14801ej3v1ud 149 figure 9-11. 3-wire serial i/o mode timing (7/7) (xii) slave operation (when dap20 = 1, ckp20 = 1, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 note 2 sck20 si20 note 1 so20 hi-z hi-z ss20 sio20 write intcsi20 notes 1. the value of the last bit previously output is output. 2. do0 is output until ss20 rises. when ss20 is high, so20 is in a high-impedance state. (3) transfer start serial transfer is started by setting transfer data to the transmit shift regist er (txs20/sio20) when the following two conditions are satisfied. ? serial operation mode register 20 (csim20) bit 7 (csie20) = 1 ? internal serial clock is stopped or sck 20 is high after 8-bit serial transfer. caution if csie20 is set to "1" after data is written to txs20/ sio20, transfer does not start. the termination of 8-bit transfer stops the serial tr ansfer automatically and generat es the interrupt request signal (intcsi20).
user?s manual u14801ej3v1ud 150 chapter 10 interrupt functions 10.1 interrupt function types the following two types of in terrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally even if interrupts are disabled. it does not undergo interrupt priority control and is given top priori ty over all other interrupt requests. a standby release signal is generated. an interrupt from the watchdog timer is the only non-maskable interrupt source. (2) maskable interrupt these interrupts undergo mask control. if two or more interrupts are si multaneously generated, each interrupt has a predetermined priori ty as shown in table 10-1. a standby release signal is generated. there are three external sources and five internal sources of maskable interrupts. 10.2 interrupt sources and configuration there are a total of 9 non-maskable and maskable interrupt sources (see table 10-1 ).
chapter 10 interrupt functions user?s manual u14801ej3v1ud 151 table 10-1. interrupt sources interrupt source interrupt type priority note 1 name trigger internal/external vector table address basic configuration type note 2 non-maskable interrupt ? intwdt watchdog timer overflow (when watchdog timer mode 1 is selected) (a) 0 intwdt watchdog timer overflow (when interval timer mode is selected) internal 0004h (b) 1 intp0 0006h 2 intp1 0008h 3 intp2 pin input edge detection external 000ah (c) intsr20 end of uart reception on serial interface 20 4 intcsi20 end of 3-wire sio transfer reception on serial interface 20 000ch 5 intst20 end of uart transmission on serial interface 20 000eh 6 inttm80 generation of match signal for 8-bit timer/event counter 80 0014h maskable interrupt 7 inttm90 generation of match signal for 16-bit timer 90 internal 0016h (b) notes 1. priority is the priority order when several maskabl e interrupt requests are gener ated at the same time. 0 is the highest and 7 is the lowest. 2. basic configuration types (a), (b), and (c) correspond to (a), (b), and (c) in figure 10-1. remark there are two interrupt sources for the wa tchdog timer (intwdt): non-maskable interrupts and maskable interrupts. either one (but not both) should be selected for actual use.
chapter 10 interrupt functions user?s manual u14801ej3v1ud 152 figure 10-1. basic configuration of interrupt function (a) internal non-maskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt mk if ie internal bus interrupt request vector table address generator standby release signal (c) external maskable interrupt mk if ie internal bus external interrupt mode register 0 (intm0) interrupt request edge detector vector table address generator standby release signal if: interrupt request flag ie: interrupt enable flag mk: interrupt mask flag
chapter 10 interrupt functions user?s manual u14801ej3v1ud 153 10.3 interrupt function control registers the interrupt functions are controlled by the following four types of registers. interrupt request flag registers 0 and 1 (if0 and if1) interrupt mask flag registers 0 and 1 (mk0 and mk1) external interrupt mode register 0 (intm0) program status word (psw) table 10-2 lists interrupt requests, the correspondi ng interrupt request flags, and interrupt mask flags. table 10-2. interrupt request signals and corresponding flags interrupt request signal interrupt request flag interrupt mask flag intwdt intp0 intp1 intp2 intsr20/intcsi20 intst20 inttm80 inttm90 wdtif pif0 pif1 pif2 srif20 stif20 tmif80 tmif90 wdtmk pmk0 pmk1 pmk2 srmk20 stmk20 tmmk80 tmmk90
chapter 10 interrupt functions user?s manual u14801ej3v1ud 154 (1) interrupt request flag regi sters 0 and 1 (if0 and if1) an interrupt request flag is set to 1 when the corres ponding interrupt request is i ssued, or when the related instruction is executed. it is cleared to 0 when t he interrupt request is acknowledged, when a reset signal is input, or when a related instruction is executed. if0 and if1 are set with a 1-bit or 8-bi t memory manipulation instruction. reset input clears if0 and if1 to 00h. figure 10-2. format of interrupt request flag register 000000 tmif90 tmif80 if1 ffe1h 00h r/w if 0 1 interrupt request flag no interrupt request signal has been issued. an interrupt request signal has been issued; an interrupt request has been made. 6 7 5432<1><0> 0 0 stif20 srif20 pif2 pif1 pif0 wdtif if0 symbol address after reset r/w ffe0h 00h r/w 6 7 <5> <4> <3> <2> <1> <0> cautions 1. bits 6 and 7 of if0 and bits 2 to 7 of if1 must all be set to 0. 2. the wdtif flag can be read- and write-accessed only when the watchdog timer is being used as an interval timer. it must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2. 3. when port 2 is being used as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as an external interrupt input. to use port 2 in output mode, therefore, the inte rrupt mask flag must be preset to 1.
chapter 10 interrupt functions user?s manual u14801ej3v1ud 155 (2) interrupt mask flag registers 0 and 1 (mk0 and mk1) the interrupt mask flags are used to enable and disable the corresponding maskable interrupts. mk0 and mk1 are set with a 1-bit or 8-bi t memory manipulation instruction. reset input sets mk0 and mk1 to ffh. figure 10-3. format of interrupt mask flag register 1 1 1 1 1 1 tmmk90 tmmk80 mk1 ffe5h ffh r/w mk 0 1 interrupt servicing control enable interrupt servicing. disable interrupt servicing. 6 7 5432<1><0> 1 stmk20 1 srmk20 pmk2 pmk1 pmk0 wdtmk mk0 symbol address after reset r/w ffe4h ffh r/w 6 7 <5> <4> <3> <2> <1> <0> cautions 1. bits 6 and 7 of mk0 and bits 2 to 7 of mk1 must all be set to 1. 2. when the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to read the wdtmk flag results in an undefined value being detected. 3. when port 2 is being used as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as an external interrupt input. to use port 2 in output mode, therefor e, the interrupt mask flag must be preset to 1.
chapter 10 interrupt functions user?s manual u14801ej3v1ud 156 (3) external interrupt m ode register 0 (intm0) intm0 is used to specify a valid edge for intp0 to intp2. intm0 is set with an 8-bit memo ry manipulation instruction. reset input clears intm0 to 00h. figure 10-4. format of external interrupt mode register 0 es21 es20 es11 es10 es01 es00 0 0 intm0 76543210 es11 0 0 1 1 intp1 valid edge selection es10 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges es21 0 0 1 1 intp2 valid edge selection es20 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges es01 0 0 1 1 intp0 valid edge selection es00 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges symbol address after reset r/w ffech 00h r/w cautions 1. bits 0 and 1 must both be set to 0. 2. before setting intm0, set the corres ponding interrupt mask flag to 1 to disable interrupts. to enable interrupts, clear to 0 the corresponding interrupt request flag, then the corresponding interrupt mask flag.
chapter 10 interrupt functions user?s manual u14801ej3v1ud 157 (4) program status word (psw) the program status word is used to hold the instruction execution resu lt and the current status of the interrupt requests. the ie flag, used to enable and di sable maskable interrupts, is mapped to the psw. the psw can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and dedicated instructions (ei and di). when a vector interrupt is ack nowledged, the psw is automatically saved to a stack, and the ie flag is reset to 0. reset input sets psw to 02h. figure 10-5. program status word configuration ie z 0 ac 0 0 1 cy psw symbol after reset 02h 76543210 ie 0 1 disabled enabled whether to enable/disable interrupt acknowledgment used in the execution of ordinary instructions
chapter 10 interrupt functions user?s manual u14801ej3v1ud 158 10.4 interrupt processing operation 10.4.1 non-maskable interrupt request acknowledgment operation the non-maskable interrupt request is unconditionally ack nowledged even when interrupts are disabled. it is not subject to interrupt priority control and takes precedence over all other interrupts. when the non-maskable interrupt request is acknowledged, t he psw and pc are saved to the stack in that order, the ie flag is reset to 0, the content s of the vector table are loaded to t he pc, and then program execution branches. figure 10-6 shows the flowchart from non-maskable inte rrupt request generation to acknowledgment. figure 10-7 shows the timing of non-maskable interrupt request a cknowledgment. figure 10-8 shows the acknowledgment operation if multiple non-mask able interrupts are generated. caution during a non-maskable interrupt servi ce program execution, do not input another non- maskable interrupt request; if it is input, th e service program will be in terrupted and the new interrupt request will be acknowledged.
chapter 10 interrupt functions user?s manual u14801ej3v1ud 159 figure 10-6. flowchart from non-maskable in terrupt request genera tion to acknowledgment start wdtm4 = 1 (watchdog timer mode is selected) interval timer no wdt overflows no yes reset processing no yes yes interrupt request is generated interrupt servicing is started wdtm3 = 0 (non-maskable interrupt is selected) wdtm: watchdog timer mode register wdt: watchdog timer figure 10-7. timing of non-maskable interrupt request acknowledgment instruction instruction saving psw and pc, and jump to interrupt servicing interrupt servicing program cpu processing wdtif figure 10-8. acknowledgment of non-maskable interrupt request second interrupt servicing first interrupt servicing nmi request (second) nmi request (first) main routine
chapter 10 interrupt functions user?s manual u14801ej3v1ud 160 10.4.2 maskable interrupt re quest acknowledgment operation a maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. a vect ored interrupt request is a cknowledged in the interrupt enabled status (when the ie flag is set to 1). the time required to start the inte rrupt servicing after a maskable inte rrupt request has been generated is shown in table 10-3. see figures 10-10 and 10-11 for the inte rrupt request acknowledgment timing. table 10-3. time from generation of maskable interrupt request to servicing minimum time maximum time note 9 clocks 19 clocks note the wait time is maximum when an interrupt request is generated imm ediately before bt and bf instruction. remark 1 clock: (f cpu : cpu clock) when two or more maskable interrupt requests are generat ed at the same time, they are acknowledged starting from the interrupt request assigned the highest priority. a pending interrupt is acknowledged when a status in which it can be acknowledged is set. figure 10-9 shows the algorithm of interrupt requests acknowledgment. when a maskable interrupt request is a cknowledged, the contents of the psw and pc are saved to the stack in that order, the ie flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the pc, and execution branches. to return from interrupt servic ing, use the reti instruction. 1 f cpu
chapter 10 interrupt functions user?s manual u14801ej3v1ud 161 figure 10-9. interrupt request acknowledgment processing algorithm start if = 1 ? mk = 0 ? ie = 1 ? vectored interrupt servicing yes (interrupt request generated) yes yes no no no interrupt request pending interrupt request pending if: interrupt request flag mk: interrupt mask flag ie: flag to control maskable interrupt reques t acknowledgment (1 = enable, 0 = disable)
chapter 10 interrupt functions user?s manual u14801ej3v1ud 162 figure 10-10. interrupt request ackno wledgment timing (example of mov a,r) clock cpu interrupt mov a,r saving psw and pc, jump to interrupt servicing 8 clocks interrupt servicing program if an interrupt request flag ( if) is set before an instruction clock n (n = 4 to 10) under execution becomes n ? 1, the interrupt is acknowledged after the instruction under execution is comple te. figure 10-10 shows an example of the interrupt request acknowledgment timing for an 8-bit data transfer instruction mo v a,r. since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgment processing is performed after the mo v a,r instruction is executed. figure 10-11. interrupt request ack nowledgment timing (when interrupt request flag is set at last clock during instruction execution) saving psw and pc, jump to interrupt servicing 8 clocks interrupt servicing program clock cpu interrupt nop mov a,r if an interrupt request flag ( if) is set at the last clock of the in struction, the inte rrupt acknowledgment processing starts after the next instruction is exec uted. figure 10-11 shows an example of the interrupt acknowledgment timing for an interrupt reques t flag that is set at the second clo ck of nop (2-clock instruction). in this case, the mov a,r instruction a fter the nop instruction is executed, and then the interrupt acknowledgment processing is performed. caution interrupt requests are held pe nding while interrupt request flag re gister 0 or 1 (if0 or if1) or interrupt mask flag register 0 or 1 (mk0 or mk1) is being accessed. 10.4.3 multiple interrupt servicing multiple interrupt servicing, in wh ich another interrupt is acknowledged while an interrupt is being serviced, can be performed using a priority order system. when two or more interrupts are generated at onc e, interrupt servicing is performed according to the priority assi gned to each interrupt request in advance (see table 10-1 ).
chapter 10 interrupt functions user?s manual u14801ej3v1ud 163 figure 10-12. example of multiple interrupts example 1. a multiple interrupt is acknowledged intyy ei main processing ei intyy servicing intxx servicing reti ie = 0 intxx reti ie = 0 during interrupt intxx servicing, interrupt request int yy is acknowledged, and multiple interrupts are generated. the ei instruction is issued bef ore each interrupt request ackno wledgement, and the interrupt request acknowledgment enable state is set. example 2. multiple interrupts are not generated because interrupts are not enabled intyy ei main processing reti intyy servicing intxx servicing ie = 0 intxx reti intyy is held pending ie = 0 because interrupts are not enabled in inte rrupt intxx servicing (the ei instruct ion is not issued), interrupt request intyy is not acknowledged, and mult iple interrupts are not generated. the intyy request is reserved and acknowledged after the intxx servicing is performed. ie = 0: interrupt request acknowledgment disabled
chapter 10 interrupt functions user?s manual u14801ej3v1ud 164 10.4.4 interrupt request hold some instructions may hold the a cknowledgment of an instruction reques t pending until the completion of the execution of the next instruction even if the interrupt request (maskabl e interrupt, non-maskable interrupt, and external interrupt) is generated during t he execution. the following shows such instructions (interrupt request hold instructions). ? manipulation instruction for interrupt request flag registers 0 and 1 (if0 and if1) ? manipulation instruction for interrupt mask flag registers 0 and 1 (mk0 and mk1)
user?s manual u14801ej3v1ud 165 chapter 11 standby function 11.1 standby function and configuration 11.1.1 standby function the standby function is used to reduce the power consum ption of the system and can be effected in the following two modes. (1) halt mode this mode is set when the halt instru ction is executed. ha lt mode stops the operati on clock of the cpu. the system clock oscillator continues oscillating. this mode does not reduce t he power consumption as much as stop mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations. (2) stop mode this mode is set when the stop instruction is exec uted. the stop mode stops the main system clock oscillator and stops the entire system. the power consumpti on of the cpu can be s ubstantially reduced in this mode. the low voltage (v dd = 1.8 v max.) of the data memory can be reta ined. therefore, this mode is useful for retaining the contents of t he data memory at an extremel y low power consumption. stop mode can be released by an interrupt request, so that this mode can be used for intermittent operation. however, some time is required until the system clock oscilla tor stabilizes after stop mode has been released. if processing must be resumed immediatel y by using an interrupt r equest, therefore, use the halt mode. in both modes, the previous contents of the registers, flags, and data memo ry before setting standby mode are all retained. in addition, the statuses of the output latches of the i/o ports and output buffers are also retained. caution to set stop mode, be sure to stop the opera tions of the peripheral ha rdware, and then execute the stop instruction.
chapter 11 standby function user?s manual u14801ej3v1ud 166 11.1.2 standby function control register the wait time after stop mode is released upon interrupt request until the oscillation st abilizes is controlled with the oscillation stabilization time selection register (osts). osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, the o scillation stabilization time after reset input is 2 15 /f x , instead of 2 17 /f x . figure 11-1. format of oscillation st abilization time selection register osts2 0 0 1 osts1 0 1 0 osts0 0 0 0 oscillation stabilization time selection other than above 00 0 0 osts1 osts2 0 osts0 osts 7 654 32 10 symbol address after reset r/w fffah 04h r/w 2 12 /f x 2 15 /f x 2 17 /f x setting prohibited 410 s 3.28 ms 13.1 ms 819 s 6.55 ms 26.2 ms at f x = 10.0 mhz operation note at f x = 5.0 mhz operation ? note expanded-specificati on products only. caution the wait time after stop mode is released does not include the time from stop mode release to clock oscillation start ("a" in the figure belo w), regardless of whether stop mode is released by reset input or by interrupt generation. a stop mode release x1 pin voltage waveform remark f x : system clock oscillation frequency
chapter 11 standby function user?s manual u14801ej3v1ud 167 11.2 operation of standby function 11.2.1 halt mode (1) halt mode halt mode is set by execut ing the halt instruction. the operation statuses in halt mode are shown in the following table. table 11-1. operation statuses in halt mode item halt mode operation status system clock generator system clock oscillation enabled clock supply to cpu stopped cpu operation disabled port (output latch) remains in the state existing before the selection of halt mode 16-bit timer 90 operation enabled 8-bit timer/event counter 80 operation enabled watchdog timer operation enabled serial interface 20 operation enabled external interrupt operation enabled note note maskable interrupt that is not masked (2) releasing halt mode halt mode can be released by the following three sources. (a) releasing by unmasked interrupt request halt mode is released by an unm asked interrupt request. in this case, if interrupt request acknowledgment is enabled, vectored in terrupt servicing is performed. if interrupt acknowledgment is disabled, the instruction at the next address is executed. figure 11-2. releasing halt mode by interrupt halt instruction standby release signal wait wait halt mode operating mode operating mode clock oscillation remarks 1. the broken lines indicate the case where the interrupt request t hat has released standby mode is acknowledged. 2. the wait time is as follows. ? when vectored interrupt servici ng is performed: 9 to 10 clocks ? when vectored interrupt servicing is not performed: 1 to 2 clocks
chapter 11 standby function user?s manual u14801ej3v1ud 168 (b) releasing by non-maskable interrupt request halt mode is released regardless of whether interrupts are enabled or disabled, and vectored interrupt servicing is performed. (c) releasing by reset input when halt mode is released by t he reset signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution starts. figure 11-3. releasing halt mode by reset input halt instruction reset signal wait (2 15 /f x ) note reset period halt mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation note 3.28 ms (at f x = 10.0 mhz operation), 6.55 ms (at f x = 5.0 mhz operation) remark f x : system clock oscillation frequency table 11-2. operation after releasing halt mode releasing source mk ie operation 0 0 executes next address instruction. 0 1 executes interrupt servicing. maskable interrupt request 1 retains halt mode. non-maskable interrupt request ? executes interrupt servicing. reset input ? ? reset processing : don't care
chapter 11 standby function user?s manual u14801ej3v1ud 169 11.2.2 stop mode (1) setting and operation st atus of stop mode stop mode is set by execut ing the stop instruction. caution because standby mode can be released by an interrupt request si gnal, standby mode is released as soon as it is set if there is an in terrupt source whose interrupt request flag is set and interrupt mask flag is reset. when st op mode is set, therefore, halt mode is set immediately after the stop in struction has been executed, the wait time set by the oscillation stabilization time selection regist er (osts) elapses, and then the operation mode is set. the operation statuses in stop mode are shown in the following table. table 11-3. operation statuses in stop mode item stop mode operation status clock generator system clock oscillation stopped cpu operation stopped port (output latch) remains in the state existing before stop mode was set 16-bit timer 90 operation stopped 8-bit timer/event counter 80 operation enabled only when ti80 is selected for count clock watchdog timer operation stopped serial interface 20 operation enabled only when ex ternal clock is input to serial clock external interrupt operation enabled note note maskable interrupt that is not masked
chapter 11 standby function user?s manual u14801ej3v1ud 170 (2) releasing stop mode stop mode can be released by the following two sources. (a) releasing by unmasked interrupt request stop mode can be released by an unmasked interrupt request. in this case, vectored interrupt servicing is performed if interrupt acknowledgment is enabled after the oscillation stabilization time has elapsed. if interrupt acknowledgment is disabled, the instruction at the nex t address is executed. figure 11-4. releasing stop mode by interrupt stop instruction standby release signal wait (time set by osts) stop mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation remark the broken lines indicate the case where the interrupt request t hat has released standby mode is acknowledged. (b) releasing by reset input when stop mode is released by the reset signal, the reset oper ation is performed after the oscillation stabilization time has elapsed. figure 11-5. releasing stop mode by reset input stop instruction reset signal wait (2 15 /f x ) note stop mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation reset period note 3.28 ms (at f x = 10.0 mhz operation), 6.55 ms (at f x = 5.0 mhz operation) remark f x : system clock oscillation frequency table 11-4. operation after releasing stop mode releasing source mk ie operation 0 0 executes next address instruction. 0 1 executes interrupt servicing. maskable interrupt request 1 retains stop mode. reset input ? ? reset processing : don't care
user?s manual u14801ej3v1ud 171 chapter 12 reset function the following two operations are av ailable to generate reset signals. (1) external reset input by reset signal input (2) internal reset by watchdog timer program loop time detection external and internal reset have no functional differences. in both cases, program exec ution starts at the address at 0000h and 0001h by reset signal input. when a low level is input to the r eset pin or the watchdog timer overflow s, a reset is applied and each hardware is set to the status shown in tabl e 12-1. each pin is high impedance duri ng reset input or during the oscillation stabilization time just after reset clear. when a high level is input to the r eset pin, the reset is cleared and progr am execution is started after the oscillation stabilization time has elapsed. the reset appli ed by the watchdog timer overfl ow is automatically cleared after reset, and program execution is started afte r the oscillation stabilization time has elapsed (see figures 12-2 through 12-4 ). cautions 1. for an external reset, input a low level of 10 s or more to the reset pin. 2. when stop mode is cleared by reset, the st op mode contents are he ld during reset input. however, the port pins become high impedance. figure 12-1. block diagram of reset function reset interrupt function count clock reset controller watchdog timer over- flow reset signal stop
chapter 12 reset function user?s manual u14801ej3v1ud 172 figure 12-2. reset timing by reset input x1 reset internal reset signal port pin normal operation reset period (oscillation stops) oscillation stabilization time wait normal operation (reset processing) delay delay hi-z figure 12-3. reset timing by watchdog timer overflow x1 internal reset signal port pin watchdog timer overflow normal operation reset period (oscillation continues) oscillation stabilization time wait normal operation (reset processing) hi-z figure 12-4. reset timing by reset input in stop mode x1 reset internal reset signal port pin hi-z delay delay stop instruction execution normal operation stop status (oscillation stops) reset period (oscillation stops) oscillation stabilization time wait normal operation (reset processing)
chapter 12 reset function user?s manual u14801ej3v1ud 173 table 12-1. status of hardware after reset hardware status after reset program counter (pc) note 1 loaded with the contents of the reset vector table (0000h, 0001h) stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 ports (p0 to p3) (output latch) 00h port mode registers (pm0 to pm3) ffh pull-up resistor option registers (pu0, pub2) 00h processor clock control register (pcc) 02h oscillation stabilization time selection register (osts) 04h timer counter (tm90) 0000h compare register (cr90) ffffh mode control register (tmc90) 00h capture register (tcp90) undefined 16-bit timer buzzer output control register (bzc90) 00h timer counter (tm80) 00h compare register (cr80) undefined 8-bit timer/event counter mode control register (tmc80) 00h clock selection r egister (wdcs) 00h watchdog timer mode register (wdtm) 00h serial operation mode register (csim20) 00h asynchronous serial interface mode register (asim20) 00h asynchronous serial interface st atus register (asis20) 00h baud rate generator control register (brgc20) 00h transmit shift register (txs20) ffh serial interface receive buffer register (rxb20) undefined request flag registers (if0, if1) 00h mask flag registers (mk0, mk1) ffh interrupts external interrupt mode register (intm0) 00h notes 1. while a reset signal is being input, and during the osc illation stabilization period, the contents of the pc will be undefined, while the remainder of the har dware will be the same as after the reset. 2. in standby mode, the ram enter s the hold state after a reset.
user?s manual u14801ej3v1ud 174 chapter 13 pd78f9076 the pd78f9076 replaces the in ternal rom of the pd789071, 789072, 789074, 789071(a), 789072(a), and 789074(a), with flash memory. the differences between the flash memory and the mask rom versions are shown in table 13-1. table 13-1. differences between fl ash memory and mask rom versions flash memory version mask rom version item pd78f9076 pd789071 pd789071(a) pd789072 pd789072(a) pd789074 pd789074(a) rom structure flash memory mask rom rom capacity 16 kb 2 kb 4 kb 8 kb internal memory high-speed ram 256 bytes v pp pin provided not provided electrical characte ristics refer to chapter 15 electrical specifications (expanded- specification products) and chapter 16 electrical specifications (conventional products) . caution there are differences in the noise immunity and noise radiation between flash memory and mask rom versions. when pre-producing an app lication set with the flash memory version and the mass producing it with the mask rom version, be sure to conduct sufficient evaluations on the commercial sample (cs), not engineeri ng sample (es), of the mask rom version.
chapter 13 pd78f9076 user?s manual u14801ej3v1ud 175 13.1 flash memory characteristics flash memory programming is performed by connecting a dedicated flash programmer (flashpro iii (part no. fl- pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)) to the target system with the pd78f9076 mounted on the target system (on-board). a flash memory program adapter (fa adapte r), which is a target board used exclusively for programming, is also provided. remark fl-pr3, fl-pr4, and the program adapter are products made by naito densei machida mfg. co., ltd. (tel +81-45-475-4191). programming using flash memory has the following advantages. ? software can be modified after the microcontro ller is solder-mounted on the target system. ? distinguishing software facilities sm all-quantity, varied model production ? easy data adjustment when starting mass production 13.1.1 programming environment the following shows the environment required for pd78f9076 flash memory programming. when flashpro iii (part no. fl-pr3, pg-fp3) or flashpro iv (part no. fl-pr4, pg-fp4) is used as a dedicated flash programmer, a host machine is required to cont rol the dedicated flash progr ammer. communication between the host machine and flash programmer is performed via rs-232c/usb (rev. 1.1). for details, refer to the manuals for flashpro iii/flashpro iv. remark usb is supported by flashpro iv only. figure 13-1. environment for wr iting program to flash memory host machine rs-232c usb dedicated flash programmer pd78f9076 v pp v dd v ss reset 3-wire serial i/o, uart or pseudo 3-wire
chapter 13 pd78f9076 user?s manual u14801ej3v1ud 176 13.1.2 communication mode use the communication mode shown in table 13-2 to perform communication between the dedicated flash programmer and pd78f9076. table 13-2. communication mode list type setting note 1 cpu clock communication mode comm port sio clock in flashpro on target board multiple rate pins used number of v pp pulses 3-wire serial i/o sio ch-0 (3-wire, sync.) 100 hz to 1.25 mhz note 2 1, 2, 4, 5 mhz notes 2, 3 1 to 5 mhz note 2 1.0 si20/rxd20/p22 so20/txd20/p21 sck20/asck20/p20 0 uart uart ch-0 (async.) 4,800 to 76,800 bps notes 2, 4 5 mhz note 5 4.91 or 5 mhz note 2 1.0 rxd20/si20/p22 txd20/so20/p21 8 pseudo 3-wire port a (pseudo- 3 wire) 100 hz to 1 khz 1, 2, 4, 5 mhz notes 2, 3 1 to 5 mhz note 2 1.0 p01 p02 p00 12 notes 1. selection items for type settings on the dedicated flash programmer (flashpro iii (part no. fl-pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)). 2. the possible setting range differs depending on the voltage. for details, refer to chapter 15 electrical specifications (exp anded-specification products) and chapter 16 electrical specifications (conventional products) . 3. 2 or 4 mhz only for flashpro iii 4. because signal wave slew also affects uart communication, in addition to the baud rate error, thoroughly evaluate the slew. 5. only for flashpro iv. however, when using flashpro iii, be sure to select the clock of the resonator on the board. uart cannot be used with the clock supplied by flashpro iii. figure 13-2. communication mode selection format 10 v v ss v dd v pp v dd v ss reset 12 n v pp pulses
chapter 13 pd78f9076 user?s manual u14801ej3v1ud 177 figure 13-3. example of connecti on with dedicated flash programmer (a) 3-wire serial i/o dedicated flash programmer vpp1 vdd reset sck so si clk note 1 gnd v pp v dd reset sck20 si20 so20 x1 v ss pd78f9076 (b) uart dedicated flash programmer vpp1 vdd reset so si clk notes 1, 2 gnd v pp v dd reset r x d20 t x d20 x1 v ss pd78f9076 (c) pseudo 3-wire (when p0 is used) dedicated flash programmer vpp1 vdd reset sck so si gnd v pp v dd reset p00 (serial clock) p02 (serial input) p01 (serial output) clk note 1 x1 v ss pd78f9076 notes 1. when supplying the system clock from a dedicated flash programme r, connect the clk and x1 pins and cut off the resonator on the board. when using the clock oscillated by the on-board resonator, do not connect the clk pin. 2. when using uart with flashpro iii, t he clock of the resonator connect ed to the x1 pin must be used, so do not connect the clk pin. caution the v dd pin, if already connected to the power suppl y, must be connected to the vdd pin of the dedicated flash programmer. when usi ng the power supply connected to the v dd pin, supply voltage before starting programming.
chapter 13 pd78f9076 user?s manual u14801ej3v1ud 178 if flashpro iii (part no. fl-pr3, pg-fp3)/flashpro iv ( part no. fl-pr4, pg-fp4) is used as a dedicated flash programmer, the following signals are generated for the pd78f9076. for details, refer to the manual of flashpro iii/flashpro iv. table 13-3. pin connection list signal name i/o pin function pin name 3-wire serial i/o uart pseudo 3-wire vpp1 output write voltage v pp vpp2 ? ? ? vdd i/o v dd voltage generation/ voltage monitoring v dd note note note gnd ? ground v ss clk output clock output x1 reset output reset signal reset si input receive signal so20/txd20/p01 so output transmit signal si20/rxd20/p02 sck output transfer clock sck20/p00 hs input handshake signal ? note v dd voltage must be supplied befor e programming is started. remark : pin must be connected. : if the signal is supplied on the target board, pin does not need to be connected. : pin does not need to be connected.
chapter 13 pd78f9076 user?s manual u14801ej3v1ud 179 13.1.3 on-board pin connections when programming on the target system, provide a connector on the target system to connect to the dedicated flash programmer. there may be cases in which an on-board function that switches from the normal operation mode to flash memory programming mode is required. input 0 v to the v pp pin in the normal operation m ode. a writing voltage of 10.0 v (typ.) is supplied to the v pp pin in the flash memory programmi ng mode. therefore, connect the v pp pin as follows. (1) connect a pull-down resistor of rv pp = 10 k ? to the v pp pin. (2) set the jumper on the board to switch the input of v pp pin to the programmer side or directly to gnd. the following shows an example of v pp pin connection. figure 13-4 v pp pin connection example pd78f9076 v pp pull-down resistor (rv pp ) connection pin of dedicated flash programmer the following shows the pins us ed by each serial interface. serial interface pins used 3-wire serial i/o si20, so20, sck20 uart rxd20, txd20 pseudo 3-wire p00, p01, p02 note that signal conflict or malfuncti on of other devices may occur when an on- board serial interface pin that is connected to another device is connected to the dedica ted flash programmer.
chapter 13 pd78f9076 user?s manual u14801ej3v1ud 180 (1) signal conflict a signal conflict occurs if the dedica ted flash programmer (output) is c onnected to a serial interface pin (input) connected to another dev ice (output). to prevent this signal conflict, isolate t he connection with the other device or put the other devic e in the output hi gh impedance status. figure 13-5. signal conflict (serial interface input pin) pd78f9076 signal conflict output pin in the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict. to prevent this, isolate the signal on the device side. connection pin of dedicated flash programmer other device input pin (2) malfunction of another device when the dedicated flash programmer (out put or input) is connected to a seri al interface pin (input or output) connected to another device (i nput), a signal may be output to the device, causing a malfunction. to prevent such malfunction, isolate the connecti on with other device or set so that the input signal to the device is ignored. figure 13-6. malfunction of another device pd78f9076 input pin input pin pin pin other device other device connection pin of dedicated flash programmer connection pin of dedicated flash programmer if the signal output by the pd78f9076 affects another device in the flash memory programming mode, isolate the signal on the device side. if the signal output by the dedicated flash programmer affects another device, isolate the signal on the device side. pd78f9076
chapter 13 pd78f9076 user?s manual u14801ej3v1ud 181 when the reset signal of the dedicat ed flash programmer is connected to the reset signal connected to the reset signal generator on the board, a signal conflict occurs. to prevent this signal conflict, isolate the connection with the reset signal generator. if a reset signal is input from the user system in the flash memory programming mode, a normal programming operation will not be performed. do not input signals other than reset signals from the dedicated flash programmer during this period. figure 13-7. signal conflict (reset pin) reset pd78f9076 signal conflict output pin reset signal generator in the flash memory programming mode, the signal output by the reset signal generator and the signal output by the dedicated flash writer conflict, therefore, isolate the signal on the reset signal generator side connection pin of dedicated flash writer shifting to the flash memory programming mode sets all the pins except those used for flash memory programming communication to the st atus immediately after reset. therefore, if the exter nal device does not acknowledge an initial status such as t he output high impedance status, connect the external device to v dd or v ss via a resistor. when using an on-board clock, connection of x1 and x2 mu st conform to the methods in the normal operation mode. when using the clock output of the flash programmer, directly connect it to the x1 pin with the on-board oscillator disconnected, and leave the x2 pin open. to use the power output of the flash programmer, connect the v dd and v ss pins to v dd and gnd of the flash programmer, respectively. to use the on-board power supply, connec tion must conform to that in t he normal operation mode. however, because the voltage is monitored by t he flash programmer, therefore, v dd of the flash programmer must be connected.
chapter 13 pd78f9076 user?s manual u14801ej3v1ud 182 13.1.4 connection of adapter for flash writing the following figures show examples of the recommended connection when the adapter for flash writing is used. figure 13-8. wiring example for flash wr iting adapter using 3-wire serial i/o 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f9076 vdd2 (lvdd) vdd gnd si so sck clkout reset vpp writer interface reserve/hs frash vdd (2.7 to 5.5 v) gnd
chapter 13 pd78f9076 user?s manual u14801ej3v1ud 183 figure 13-9. wiring example for flash writing adapter using uart 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f9076 vdd2 (lvdd) vdd gnd si so sck clkout reset vpp writer interface reserve/hs frash vdd (2.7 to 5.5 v) gnd
chapter 13 pd78f9076 user?s manual u14801ej3v1ud 184 figure 13-10. wiring example for flash writing adapter using pseudo 3-wire 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f9076 vdd2 (lvdd) vdd gnd si so sck clkout reset vpp writer interface reserve/hs frash vdd (2.7 to 5.5 v) gnd
user?s manual u14801ej3v1ud 185 chapter 14 instruction set overview this chapter lists the instruction set of the pd789074 subseries. for details of the operation and machine language (instruction code) of each instruction, refer to 78k/0s series instructions user?s manual (u11047e) . 14.1 operation 14.1.1 operand identifier s and description methods operands are described in the "operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for det ails). when there are two or more description methods, select one of them. uppercase lette rs and the symbols #, !, $, and [ ] are keywords and are described as they are. each symbol has the following meaning. ? #: immediate dat a specification ? !: absolute address specification ? $: relative address specification ? [ ]: indirect address specification in the case of immediate data, descr ibe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for operand register identifiers, r and rp , either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 14-1. operand identifi ers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special-function register symbol saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even addresses only) addr16 addr5 0000h to ffffh immediate data or labels (only ev en addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark for symbols of special function registers, see table 3-3 special function registers .
chapter 14 instruction set overview user?s manual u14801ej3v1ud 186 14.1.2 description of "operation" column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag nmis: flag indicating non-maskable interrupt servicing in progress ( ): memory contents indicated by addre ss or register contents in parentheses h , l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 14.1.3 description of "flag" column (blank): unchanged 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is stored
chapter 14 instruction set overview user?s manual u14801ej3v1ud 187 14.2 operation list flag mnemonic operand bytes clocks operation z ac cy r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte a, r note 1 2 4 a r r, a note 1 2 4 r a a, saddr 2 4 a (saddr) saddr, a 2 4 (saddr) a a, sfr 2 4 a sfr sfr, a 2 4 sfr a a, !addr16 3 8 a (addr16) !addr16, a 3 8 (addr16) a psw, #byte 3 6 psw byte a, psw 2 4 a psw psw, a 2 4 psw a a, [de] 1 6 a (de) [de], a 1 6 (de) a a, [hl] 1 6 a (hl) [hl], a 1 6 (hl) a a, [hl + byte] 2 6 a (hl + byte) mov [hl + byte], a 2 6 (hl + byte) a a, x 1 4 a ? x a, r note 2 2 6 a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? sfr a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) xch a, [hl, byte] 2 8 a ? (hl + byte) notes 1. except r = a. 2. except r = a, x. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 14 instruction set overview user?s manual u14801ej3v1ud 188 flag mnemonic operand bytes clocks operation z ac cy rp, #word 3 6 rp word ax, saddrp 2 6 ax (saddrp) saddrp, ax 2 8 (saddrp) ax ax, rp note 1 4 ax rp movw rp, ax note 1 4 rp ax xchw ax, rp note 1 8 ax ? rp a, #byte 2 4 a, cy a + byte saddr, #byte 3 6 (saddr), cy (saddr) + byte a, r 2 4 a, cy a + r a, saddr 2 4 a, cy a + (saddr) a, !addr16 3 8 a, cy a + (addr16) a, [hl] 1 6 a, cy a + (hl) add a, [hl + byte] 2 6 a, cy a + (hl + byte) a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 (saddr), cy (saddr) + byte + cy a, r 2 4 a, cy a + r + cy a, saddr 2 4 a, cy a + (saddr) + cy a, !addr16 3 8 a, cy a + (addr16) + cy a, [hl] 1 6 a, cy a + (hl) + cy addc a, [hl + byte] 2 6 a, cy a + (hl + byte) + cy a, #byte 2 4 a, cy a ? byte saddr, #byte 3 6 (saddr), cy (saddr) ? byte a, r 2 4 a, cy a ? r a, saddr 2 4 a, cy a ? (saddr) a, !addr16 3 8 a, cy a ? (addr16) a, [hl] 1 6 a, cy a ? (hl) sub a, [hl + byte] 2 6 a, cy a ? (hl + byte) note only when rp = bc, de, or hl. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 14 instruction set overview user?s manual u14801ej3v1ud 189 flag mnemonic operand bytes clocks operation z ac cy a, #byte 2 4 a, cy a ? byte ? cy saddr, #byte 3 6 (saddr), cy (saddr) ? byte ? cy a, r 2 4 a, cy a ? r ? cy a, saddr 2 4 a, cy a ? (saddr) ? cy a, !addr16 3 8 a, cy a ? (addr16) ? cy a, [hl] 1 6 a, cy a ? (hl) ? cy subc a, [hl + byte] 2 6 a, cy a ? (hl + byte) ? cy a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) and a, [hl + byte] 2 6 a a (hl + byte) a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) or a, [hl + byte] 2 6 a a (hl + byte) a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) xor a, [hl + byte] 2 6 a a (hl + byte) remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 14 instruction set overview user?s manual u14801ej3v1ud 190 flag mnemonic operand bytes clocks operation z ac cy a, #byte 2 4 a ? byte saddr, #byte 3 6 (saddr) ? byte a, r 2 4 a ? r a, saddr 2 4 a ? (saddr) a, !addr16 3 8 a ? (addr16) a, [hl] 1 6 a ? (hl) cmp a, [hl + byte] 2 6 a ? (hl + byte) addw ax, #word 3 6 ax, cy ax + word subw ax, #word 3 6 ax, cy ax ? word cmpw ax, #word 3 6 ax ? word r 2 4 r r + 1 inc saddr 2 4 (saddr) (saddr) + 1 r 2 4 r r ? 1 dec saddr 2 4 (saddr) (saddr) ? 1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ? 1 ror a, 1 1 2 (cy, a 7 a 0 , a m ? 1 a m ) 1 rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1 rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ? 1 a m ) 1 rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 3 6 psw.bit 1 set1 [hl].bit 2 10 (hl).bit 1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 3 6 psw.bit 0 clr1 [hl].bit 2 10 (hl).bit 0 set1 cy 1 2 cy 1 1 clr1 cy 1 2 cy 0 0 not1 cy 1 2 cy cy remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 14 instruction set overview user?s manual u14801ej3v1ud 191 flag mnemonic operand bytes clocks operation z ac cy call !addr16 3 6 (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callt [addr5] 1 8 (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 ret 1 6 pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 8 pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3, nmis 0 r r r psw 1 2 (sp ? 1) psw, sp sp ? 1 push rp 1 4 (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 4 psw (sp), sp sp + 1 r r r pop rp 1 6 rp h (sp + 1), rp l (sp), sp sp + 2 sp, ax 2 8 sp ax movw ax, sp 2 6 ax sp !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 br ax 1 6 pc h a, pc l x bc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 0 saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 bt psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 1 saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 bf psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 0 b, $addr16 2 6 b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ? 1, then pc pc + 2 + jdisp8 if c 0 dbnz saddr, $addr16 3 8 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 nop 1 2 no operation ei 3 6 ie 1 (enable interrupt) di 3 6 ie 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 14 instruction set overview user?s manual u14801ej3v1ud 192 14.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, push, pop, dbnz 2nd operand 1st operand #byte a r sfr saddr ! addr16 psw [de] [hl] [hl + byte] $addr16 1 none a add addc sub subc and or xor cmp mov note xch note add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov [hl + byte] mov note except r = a.
chapter 14 instruction set overview user?s manual u14801ej3v1ud 193 (2) 16-bit instructions movw, xchw, addw, subw, cmpw , push, pop, incw, decw 2nd operand 1st operand #word ax rp note saddrp sp none ax addw subw cmpw movw xchw movw movw rp movw movw note incw decw push pop saddrp movw sp movw note only when rp = bc, de, or hl. (3) bit manipulation instructions set1, clr1, not1, bt, bf 2nd operand 1st operand $addr16 none a.bit bt bf set1 clr1 sfr.bit bt bf set1 clr1 saddr.bit bt bf set1 clr1 psw.bit bt bf set1 clr1 [hl].bit set1 clr1 cy set1 clr1 not1
chapter 14 instruction set overview user?s manual u14801ej3v1ud 194 (4) call instructions/branch instructions call, callt, br, bc, bnc, bz, bnz, dbnz 2nd operand 1st operand ax !addr16 [addr5] $addr16 basic instructions br call br callt br bc bnc bz bnz compound instructions dbnz (5) other instructions ret, reti, nop, ei, di, halt, stop
user?s manual u14801ej3v1ud 195 chapter 15 electrical specificatio ns (expanded-specif ication products) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ? 0.3 to +6.5 v v pp pd78f9076 only, note ? 0.3 to +10.5 v input voltage v i ? 0.3 to v dd + 0.3 v output voltage v o ? 0.3 to v dd + 0.3 v per pin ? 10 ma total for all pins pd78907x, 78f9076 ? 30 ma per pin ? 7 ma output current, high i oh total for all pins pd78907x(a) ? 22 ma per pin 30 ma total for all pins pd78907x, 78f9076 160 ma per pin 10 ma output current, low i ol total for all pins pd78907x(a) 120 ma operating ambient temperature t a during normal operation ? 40 to +85 c during flash memory programming 10 to 40 c storage temperature t stg mask rom version ? 65 to +150 c pd78f9076 ? 40 to +125 c note make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit va lue (1.8 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit val ue (1.8 v) of the operating voltage range of v dd (see b in the figure below). 1.8 v v dd 0 v 0 v v pp 1.8 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, a nd therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 15 electrical specificatio ns (expanded-specif ication products) user?s manual u14801ej3v1ud 196 system clock oscilla tor characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit v dd = 4.5 to 5.5 v 1.0 10.0 mhz oscillation frequency (f x ) note 1 v dd = 3.0 to 5.5 v 1.0 6.0 mhz v dd = 1.8 to 5.5 v 1.0 5.0 mhz 4 ms ceramic resonator x2 x1 v ss c2 c1 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. v dd = 4.5 to 5.5 v 1.0 10.0 mhz oscillation frequency (f x ) note 1 v dd = 3.0 to 5.5 v 1.0 6.0 mhz v dd = 1.8 to 5.5 v 1.0 5.0 mhz v dd = 4.5 to 5.5 v 10 ms crystal resonator x2 x1 v ss c2 c1 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 30 ms v dd = 4.5 to 5.5 v 1.0 10.0 mhz x1 input frequency (f x ) note 1 v dd = 3.0 to 5.5 v 1.0 6.0 mhz v dd = 1.8 to 5.5 v 1.0 5.0 mhz v dd = 4.5 to 5.5 v 45 500 ns v dd = 3.0 to 5.5 v 75 500 ns external clock x1 x2 x1 input high-/low-level width (t xh , t xl ) v dd = 1.8 to 5.5 v 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz x1 x2 open x1 input high-/low-level width (t xh , t xl ) v dd = 2.7 to 5.5 v 85 500 ns notes 1. indicates only oscillator c haracteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use the resonator that stabilizes oscillation within the oscillation wait time. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an ad verse effect from wiring capacitance. ? keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the o scillator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator.
chapter 15 electrical specificatio ns (expanded-specif ication products) user?s manual u14801ej3v1ud 197 recommended oscillator constant ceramic resonator (t a = ?40 to +85c) (mask rom version) recommended circuit constant (pf) oscillation voltage range (v dd ) remarks manufacturer part number frequency (mhz) c1 c2 min. max. csbla1m00j58-b0 note csbfb1m00j58-r1 note 1.0 100 100 1.9 rd = 1.0 k ? cstcc2m00g56-r0 cstcc2m00g56-r0 2.0 cstcr4m00g53-r0 cstls4m00gg53-b0 4.0 cstcr4m19g53-r0 cstls4m19gg53-b0 4.194 cstcr4m91g53-r0 cstls4m91gg53-b0 4.915 cstcr5m00g53-r0 cstls5m00gg53-b0 5.0 1.8 cstcr6m00g53-r0 cstls6m00gg53-b0 6.0 1.9 cstce8m00g52-r0 1.8 cstls8m00g53-b0 8.0 2.0 cstce8m38g52-r0 1.8 cstls8m38g53-b0 8.388 2.0 cstce10m0g52-r0 1.8 murata mfg. co., ltd. (standard product) cstls10m0g53-b0 10.0 ? ? 2.0 5.5 on-chip capacitor cstcr6m00g53093-r0 cstls6m00gg53093-b0 6.0 cstls8m00g53093-b0 8.0 cstls8m38g53093-b0 8.388 murata mfg. co., ltd. (low- voltage drive type) cstls10m0g53093-b0 10.0 ? ? 1.8 5.5 on-chip capacitor note a limiting resistor (rd = 1.0 k ? ) is required when csbla1m00j58-b0 or csbfb1m00j58-r1 (1.0 mhz) manufactured by murata mfg. co., ltd. is used as the ceramic resonator (s ee the figure below). this is not necessary when using one of t he other recommended resonators. x2 x1 c2 c1 csbla1m00j58-b0 csbfb1m00j58-r1 rd caution the oscillator cons tant is a reference value based on evalua tion in specific environments by the resonator manufacturer. if the oscillator charact eristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicat e the characteristics of the oscillator. use the intern al operation conditions of the pd789071, 789072, and 789074 within the specifications of the dc and ac characteristics.
chapter 15 electrical specificatio ns (expanded-specif ication products) user?s manual u14801ej3v1ud 198 ceramic resonator (t a = ?40 to +85c) ( pd78f9076) recommended circuit constant (pf) oscillation voltage range (v dd ) remarks manufacturer part number frequency (mhz) c1 c2 min. max. csbla1m00j58-b0 note csbfb1m00j58-r1 note 1.0 100 100 2.1 rd = 1.0 k ? cstcc2m00g56-r0 cstls2m00g56-b0 2.0 cstcr4m00g53-r0 cstls4m00gg53-b0 4.0 cstcr4m19g53-r0 cstls4m19gg53-b0 4.194 ? ? 1.9 5.5 cstcr4m91g53-r0 cstls4m91gg53-b0 4.915 cstcr5m00g53-r0 cstls5m00gg53-b0 5.0 2.0 cstcr6m00g53-r0 cstls6m00gg53-b0 6.0 2.1 cstce8m00g52-r0 1.8 cstls8m00g53-b0 8.0 2.2 cstce8m38g52-r0 1.8 cstls8m38g53-b0 8.388 2.2 cstce10m0g52-r0 2.0 murata mfg. co., ltd. cstls10m0g53-b0 10.0 2.1 on-chip capacitor cstcr4m00g53093-r0 cstls4m00gg53093-b0 4.0 cstcr4m19g53093-r0 cstls4m19gg53093-b0 4.194 cstcr4m91g53093-r0 cstls4m91gg53093-b0 4.915 cstcr5m00g53093-r0 cstls5m00gg53093-b0 5.0 cstcr6m00g53093-r0 cstls6m00gg53093-b0 6.0 cstls8m00g53093-b0 8.0 cstls8m38g53093-b0 8.388 murata mfg. co., ltd. (low- voltage drive type) cstls10m0g53u-b0 10.0 ? ? 1.8 5.5 on-chip capacitor note a limiting resistor (rd = 1.0 k ? ) is required when csbla1m00j58-b0 or csbfb1m00j58-r1 (1.0 mhz) manufactured by murata mfg. co., ltd. is used as the ceramic resonator (s ee the figure below). this is not necessary when using one of t he other recommended resonators. x2 x1 c2 c1 csbla1m00j58-b0 csbfb1m00j58-r1 rd
chapter 15 electrical specificatio ns (expanded-specif ication products) user?s manual u14801ej3v1ud 199 caution the oscillator cons tant is a reference value based on evalua tion in specific environments by the resonator manufacturer. if the oscillator charact eristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicat e the characteristics of the oscillator. use the intern al operation conditions of the pd78f9076 within the specifications of the dc and ac characteristics.
chapter 15 electrical specificatio ns (expanded-specif ication products) user?s manual u14801ej3v1ud 200 dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit i oh per pin ? 1 ma total for all pins pd78907x, 78f9076 ? 15 ma per pin ? 1 ma output current, high total for all pins pd78907x(a) ? 11 ma per pin 10 ma total for all pins pd78907x, 78f9076 80 ma i ol per pin 3 ma output current, low total for all pins pd78907x(a) 60 ma v ih1 p00 to p07, p10 to p15, v dd = 2.7 to 5.5 v 0.7v dd v dd v p30, p31 v dd = 1.8 to 5.5 v 0.9v dd v dd v v ih2 reset, p20 to p27 v dd = 2.7 to 5.5 v 0.8v dd v dd v v dd = 1.8 to 5.5 v 0.9v dd v dd v input voltage, high v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v v ih3 x1, x2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v il1 p00 to p07, p10 to p15, v dd = 2.7 to 5.5 v 0 0.3v dd v p30, p31 v dd = 1.8 to 5.5 v 0 0.1v dd v v il2 reset, p20 to p27 v dd = 2.7 to 5.5 v 0 0.2v dd v v dd = 1.8 to 5.5 v 0 0.1v dd v input voltage, low v il3 v dd = 4.5 to 5.5 v 0 0.4 v x1, x2 v dd = 1.8 to 5.5 v 0 0.1 v v dd = 4.5 to 5.5 v, i oh = ? 1 ma v dd ? 1.0 v output voltage, high v oh v dd = 1.8 to 5.5 v, i oh = ? 100 a v dd ? 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78907x, 78f9076) 1.0 v v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78907x(a)) 1.0 v output voltage, low v ol v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v i lih1 v in = v dd pins other than x1, x2 3 a input leakage current, high i lih2 x1, x2 20 a i lil1 pins other than x1, x2 ? 3 a input leakage current, low i lil2 v in = 0 v x1, x2 ? 20 a output leakage current, high i loh v out = v dd 3 a output leakage current, low i lol v out = 0 v ? 3 a software pull-up resistor r 1 v in = 0 v 50 100 200 k ? remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 15 electrical specificatio ns (expanded-specif ication products) user?s manual u14801ej3v1ud 201 dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit 10.0 mhz crystal oscillation operating mode v dd = 5.0 v 10% note 2 3.0 7.5 ma 6.0 mhz crystal oscillation operating mode v dd = 5.0 v 10% note 2 1.7 3.9 ma v dd = 5.0 v 10% note 2 1.3 2.6 ma v dd = 3.0 v 10% note 3 0.26 0.5 ma i dd1 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.14 0.30 ma 10.0 mhz crystal oscillation halt mode v dd = 5.0 v 10% note 2 1.0 2.0 ma i dd2 6.0 mhz crystal oscillation halt mode v dd = 5.0 v 10% note 2 0.8 1.6 ma v dd = 5.0 v 10% note 2 0.5 1.0 ma v dd = 3.0 v 10% note 3 0.17 0.35 ma 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.08 0.2 ma v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5.0 a power supply current note 1 (mask rom version) i dd3 stop mode v dd = 2.0 v 10% 0.05 3.0 a 10.0 mhz crystal oscillation operating mode v dd = 5.0 v 10% note 2 9.0 18.0 ma 6.0 mhz crystal oscillation operating mode v dd = 5.0 v 10% note 2 5.0 10.0 ma v dd = 5.0 v 10% note 2 4.0 8.0 ma v dd = 3.0 v 10% note 3 1.0 2.5 ma i dd1 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.8 2.0 ma 10.0 mhz crystal oscillation halt mode v dd = 5.0 v 10% note 2 1.2 6.0 ma 6.0 mhz crystal oscillation halt mode v dd = 5.0 v 10% note 2 0.9 2.8 ma v dd = 5.0 v 10% note 2 0.8 2.5 ma v dd = 3.0 v 10% note 3 0.5 2.0 ma i dd2 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.3 1.0 ma v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5.0 a power supply current note 1 ( pd78f9076) i dd3 stop mode v dd = 2.0 v 10% 0.05 3.0 a notes 1. the port current (including the current flowing th rough the on-chip pull-up resi stors) is not included. 2. high-speed mode operation (when processor clock control register (pcc) is set to 00h) 3. low-speed mode operation (when pcc is set to 02h) remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 15 electrical specificatio ns (expanded-specif ication products) user?s manual u14801ej3v1ud 202 ac characteristics (1) basic operation (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 4.5 to 5.5 v 0.2 8 s v dd = 3.0 to 5.5 v 0.33 8 s v dd = 2.7 to 5.5 v 0.4 8 s cycle time (minimum instruction execution time) t cy v dd = 1.8 to 5.5 v 1.6 8 s v dd = 2.7 to 5.5 v 0 4 mhz ti80 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz v dd = 2.7 to 5.5 v 0.1 s ti80 input high- /low-level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s interrupt input high- /low-level width t inth , t intl intp0 to intp2 10 s reset input low-level width t rsl 10 s cpt90 input high- /low-level width t cph , t cpl 10 s t cy vs v dd supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operation range
chapter 15 electrical specificatio ns (expanded-specif ication products) user?s manual u14801ej3v1ud 203 (2) serial interface (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (sck20...internal clock) parameter symbol conditions min. typ. max. unit t kcy1 v dd = 2.7 to 5.5 v 800 ns sck20 cycle time v dd = 1.8 to 5.5 v 3,200 ns t kh1 , t kl1 v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck20 high-/low- level width v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns t sik1 v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) v dd = 1.8 to 5.5 v 500 ns t ksi1 v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) v dd = 1.8 to 5.5 v 600 ns t kso1 v dd = 2.7 to 5.5 v 0 250 ns delay time from sck20 to so20 output r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1,000 ns note r and c are the load resistance and load capacitance of the so20 output line. (b) 3-wire serial i/o mode (sck20...external clock) parameter symbol conditions min. typ. max. unit t kcy2 v dd = 2.7 to 5.5 v 800 ns sck20 cycle time v dd = 1.8 to 5.5 v 3,200 ns t kh2 , t kl2 v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width v dd = 1.8 to 5.5 v 1,600 ns t sik2 v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) v dd = 1.8 to 5.5 v 150 ns t ksi2 v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns delay time from sck20 to so20 output t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (when using ss20, to ss20 ) t kas2 v dd = 1.8 to 5.5 v 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (when using ss20, from ss20 ) t kds2 v dd = 1.8 to 5.5 v 800 ns note r and c are the load resistance and load capacitance of the so20 output line.
chapter 15 electrical specificatio ns (expanded-specif ication products) user?s manual u14801ej3v1ud 204 (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate v dd = 2.7 to 5.5 v 78,125 bps v dd = 1.8 to 5.5 v 19,531 bps (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit t kcy3 v dd = 2.7 to 5.5 v 800 ns asck20 cycle time v dd = 1.8 to 5.5 v 3,200 ns t kh3 , t kl3 v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width v dd = 1.8 to 5.5 v 1,600 ns transfer rate v dd = 2.7 to 5.5 v 39,063 bps v dd = 1.8 to 5.5 v 9,766 bps t r , t f 1 s asck20 rise/fall time
chapter 15 electrical specificatio ns (expanded-specif ication products) user?s manual u14801ej3v1ud 205 ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing ti timing t tih t til ti80 1/f ti interrupt input timing intp0 to intp2 t intl t inth reset input timing reset t rsl cpt90 input timing 1/f x t xl t xh x1 input v ih3 (min.) v il3 (max.) t cpl t cph cpt90
chapter 15 electrical specificatio ns (expanded-specif ication products) user?s manual u14801ej3v1ud 206 serial transfer timing 3-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 remark m = 1, 2 3-wire serial i/o mode (when using ss20): uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3 t kas2 so20 ss20 output data t kds2
chapter 15 electrical specificatio ns (expanded-specif ication products) user?s manual u14801ej3v1ud 207 data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x ms oscillation stabilization wait time note 1 t wait release by interrupt request note 2 ms notes 1. oscillation stabilization wait time is the time in which the cpu operation is stopped to prevent unstable operation when oscillation is started. 2. selection of 2 12 /f x , 2 15 /f x , and 2 17 /f x is possible using bits 0 to 2 (o sts0 to osts2) of the oscillation stabilization time select register (osts). remark f x : system clock oscillation frequency data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operation mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode release by interrupt signal) v dd data retention mode stop mode halt mode operation mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
chapter 15 electrical specificatio ns (expanded-specif ication products) user?s manual u14801ej3v1ud 208 flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 1.0 5 mhz operating frequency f x v dd = 1.8 to 5.5 v 1.0 1.25 mhz write current note (v dd pin) i ddw when v pp supply voltage = v pp1 during f x = 5.0 mhz operation 18 ma write current note (v pp pin) i ppw when v pp supply voltage = v pp1 7.5 ma erase current note (v dd pin) i dde when v pp supply voltage = v pp1 during f x = 5.0 mhz operation 18 ma erase current note (v pp pin) i ppe when v pp supply voltage = v pp1 100 ma unit erase time t er 0.5 1 1 s total erase time t era 20 s write count erase/write are regarded as 1 cycle 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v note the port current (including the cu rrent that flows to the on-chip pull-up resistors) is not included.
user?s manual u14801ej3v1ud 209 chapter 16 electrical specifi cations (conventional products) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ? 0.3 to +6.5 v v pp pd78f9076 only, note ? 0.3 to +10.5 v input voltage v i ? 0.3 to v dd + 0.3 v output voltage v o ? 0.3 to v dd + 0.3 v per pin ? 10 ma total for all pins pd78907x, 78f9076 ? 30 ma per pin ? 7 ma output current, high i oh total for all pins pd78907x(a) ? 22 ma per pin 30 ma total for all pins pd78907x, 78f9076 160 ma per pin 10 ma output current, low i ol total for all pins pd78907x(a) 120 ma operating ambient temperature t a during normal operation ? 40 to +85 c during flash memory programming 10 to 40 c storage temperature t stg mask rom version ? 65 to +150 c pd78f9076 ? 40 to +125 c note make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit va lue (1.8 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit val ue (1.8 v) of the operating voltage range of v dd (see b in the figure below). 1.8 v v dd 0 v 0 v v pp 1.8 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, a nd therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 16 electrical specifi cations (conventional products) user?s manual u14801ej3v1ud 210 system clock oscilla tor characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 v dd = oscillation voltage range 1.0 5.0 mhz ceramic resonator x2 x1 v ss c2 c1 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms oscillation frequency (f x ) note 1 1.0 5.0 mhz v dd = 4.5 to 5.5 v 10 ms crystal resonator x2 x1 v ss c2 c1 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 30 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz x1 x2 x1 input high-/low-level width (t xh , t xl ) 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock x1 x2 open x1 input high-/low-level width (t xh , t xl ) v dd = 2.7 to 5.5 v 85 500 ns notes 1. indicates only oscillator c haracteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use the resonator that stabilizes oscillation within the oscillation wait time. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an ad verse effect from wiring capacitance. ? keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the o scillator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator.
chapter 16 electrical specifi cations (conventional products) user?s manual u14801ej3v1ud 211 recommended oscillator constant ceramic resonator (t a = ?40 to +85c) (mask rom version) recommended circuit constant (pf) oscillation voltage range (v dd ) remarks manufacturer part number frequency (mhz) c1 c2 min. max. csbla1m00j58-b0 note csbfb1m00j58-r1 note 1.0 100 100 1.9 rd = 1.0 k ? cstcc2m00g56-r0 cstls2m00g56-b0 2.0 cstcr4m00g53-r0 cstls4m00gg53-b0 4.0 cstcr4m19g53-r0 cstls4m19gg53-b0 4.194 cstcr4m91g53-r0 cstls4m91gg53-b0 4.915 cstcr5m00g53-r0 murata mfg. co., ltd. (standard product) cstls5m00gg53-b0 5.0 ? ? 1.8 5.5 on-chip capacitor note a limiting resistor (rd = 1.0 k ? ) is required when csbla1m00j58-b0 or csbfb1m00j58-r1 (1.0 mhz) manufactured by murata mfg. co., ltd. is used as the ceramic resonator (s ee the figure below). this is not necessary when using one of t he other recommended resonators. x2 x1 c2 c1 csbla1m00j58-b0 csbfb1m00j58-r1 rd caution the oscillator cons tant is a reference value based on evalua tion in specific environments by the resonator manufacturer. if the oscillator charact eristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicat e the characteristics of the oscillator. use the intern al operation conditions of the pd789071, 789072, and 789074 within the specifications of the dc and ac characteristics.
chapter 16 electrical specifi cations (conventional products) user?s manual u14801ej3v1ud 212 ceramic resonator (t a = ?40 to +85c) ( pd78f9076) recommended circuit constant (pf) oscillation voltage range (v dd ) remarks manufacturer part number frequency (mhz) c1 c2 min. max. csbla1m00j58-b0 note csbfb1m00j58-r1 note 1.0 100 100 2.1 rd = 1.0 k ? cstcc2m00g56-r0 cstls2m00g56-b0 2.0 cstcr4m00g53-r0 cstls4m00gg53-b0 4.0 cstcr4m19g53-r0 cstls4m19gg53-b0 4.194 ? ? 1.9 5.5 cstcr4m91g53-r0 cstls4m91gg53-b0 4.915 cstcr5m00g53-r0 murata mfg. co., ltd. cstls5m00gg53-b0 5.0 2.0 on-chip capacitor cstcr4m00g53093-r0 cstls4m00gg53093-b0 4.0 cstcr4m19g53093-r0 cstls4m19gg53093-b0 4.194 cstcr4m91g53093-r0 cstls4m91gg53093-b0 4.915 cstcr5m00g53093-r0 murata mfg. co., ltd. (low- voltage drive type) cstls5m00gg53093-b0 5.0 ? ? 1.8 5.5 on-chip capacitor note a limiting resistor (rd = 1.0 k ? ) is required when csbla1m00j58-b0 or csbfb1m00j58-r1 (1.0 mhz) manufactured by murata mfg. co., ltd. is used as the ceramic resonator (s ee the figure below). this is not necessary when using one of t he other recommended resonators. x2 x1 c2 c1 csbla1m00j58-b0 csbfb1m00j58-r1 rd caution the oscillator cons tant is a reference value based on evalua tion in specific environments by the resonator manufacturer. if the oscillator charact eristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicat e the characteristics of the oscillator. use the intern al operation conditions of the pd78f9076 within the specifications of the dc and ac characteristics.
chapter 16 electrical specifi cations (conventional products) user?s manual u14801ej3v1ud 213 dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit i oh per pin ? 1 ma total for all pins pd78907x, 78f9076 ? 15 ma per pin ? 1 ma output current, high total for all pins pd78907x(a) ? 11 ma per pin 10 ma total for all pins pd78907x, 78f9076 80 ma i ol per pin 3 ma output current, low total for all pins pd78907x(a) 60 ma v ih1 p00 to p07, p10 to p15, v dd = 2.7 to 5.5 v 0.7v dd v dd v p30, p31 v dd = 1.8 to 5.5 v 0.9v dd v dd v v ih2 reset, p20 to p27 v dd = 2.7 to 5.5 v 0.8v dd v dd v v dd = 1.8 to 5.5 v 0.9v dd v dd v input voltage, high v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v v ih3 x1, x2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v il1 p00 to p07, p10 to p15, v dd = 2.7 to 5.5 v 0 0.3v dd v p30, p31 v dd = 1.8 to 5.5 v 0 0.1v dd v v il2 reset, p20 to p27 v dd = 2.7 to 5.5 v 0 0.2v dd v v dd = 1.8 to 5.5 v 0 0.1v dd v input voltage, low v il3 v dd = 4.5 to 5.5 v 0 0.4 v x1, x2 v dd = 1.8 to 5.5 v 0 0.1 v v dd = 4.5 to 5.5 v, i oh = ? 1 ma v dd ? 1.0 v output voltage, high v oh v dd = 1.8 to 5.5 v, i oh = ? 100 a v dd ? 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78907x,78f9076) 1.0 v v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78907x(a)) 1.0 v output voltage, low v ol v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v i lih1 v in = v dd pins other than x1, x2 3 a input leakage current, high i lih2 x1, x2 20 a i lil1 pins other than x1, x2 ? 3 a input leakage current, low i lil2 v in = 0 v x1, x2 ? 20 a output leakage current, high i loh v out = v dd 3 a output leakage current, low i lol v out = 0 v ? 3 a software pull-up resistor r 1 v in = 0 v 50 100 200 k ? remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 16 electrical specifi cations (conventional products) user?s manual u14801ej3v1ud 214 dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 2 1.3 2.6 ma v dd = 3.0 v 10% note 3 0.26 0.5 ma i dd1 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.14 0.30 ma v dd = 5.0 v 10% note 2 0.5 1.0 ma v dd = 3.0 v 10% note 3 0.17 0.35 ma i dd2 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.08 0.2 ma v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5.0 a power supply current note 1 (mask rom version) i dd3 stop mode v dd = 2.0 v 10% 0.05 3.0 a v dd = 5.0 v 10% note 2 4.0 8.0 ma v dd = 3.0 v 10% note 3 1.0 2.5 ma i dd1 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.8 2.0 ma v dd = 5.0 v 10% note 2 0.8 2.5 ma v dd = 3.0 v 10% note 3 0.5 2.0 ma i dd2 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.3 1.0 ma v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5.0 a power supply current note 1 ( pd78f9076) i dd3 stop mode v dd = 2.0 v 10% 0.05 3.0 a notes 1. the port current (including the current flowing th rough the on-chip pull-up resi stors) is not included. 2. high-speed mode operation (when processor clock control register (pcc) is set to 00h) 3. low-speed mode operation (when pcc is set to 02h) remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 16 electrical specifi cations (conventional products) user?s manual u14801ej3v1ud 215 ac characteristics (1) basic operation (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 8 s cycle time (minimum instruction execution time) t cy v dd = 1.8 to 5.5 v 1.6 8 s v dd = 2.7 to 5.5 v 0 4 mhz ti80 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz v dd = 2.7 to 5.5 v 0.1 s ti80 input high- /low-level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s interrupt input high- /low-level width t inth , t intl intp0 to intp2 10 s reset input low-level width t rsl 10 s cpt90 input high- /low-level width t cph , t cpl 10 s t cy vs v dd supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operation range
chapter 16 electrical specifi cations (conventional products) user?s manual u14801ej3v1ud 216 (2) serial interface (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (sck20...internal clock) parameter symbol conditions min. typ. max. unit t kcy1 v dd = 2.7 to 5.5 v 800 ns sck20 cycle time v dd = 1.8 to 5.5 v 3,200 ns t kh1 , t kl1 v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck20 high-/low- level width v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns t sik1 v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) v dd = 1.8 to 5.5 v 500 ns t ksi1 v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) v dd = 1.8 to 5.5 v 600 ns t kso1 v dd = 2.7 to 5.5 v 0 250 ns delay time from sck20 to so20 output r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1,000 ns note r and c are the load resistance and load capacitance of the so20 output line. (b) 3-wire serial i/o mode (sck20...external clock) parameter symbol conditions min. typ. max. unit t kcy2 v dd = 2.7 to 5.5 v 800 ns sck20 cycle time v dd = 1.8 to 5.5 v 3,200 ns t kh2 , t kl2 v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width v dd = 1.8 to 5.5 v 1,600 ns t sik2 v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) v dd = 1.8 to 5.5 v 150 ns t ksi2 v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns delay time from sck20 to so20 output t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (when using ss20, to ss20 ) t kas2 v dd = 1.8 to 5.5 v 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (when using ss20, from ss20 ) t kds2 v dd = 1.8 to 5.5 v 800 ns note r and c are the load resistance and load capacitance of the so20 output line.
chapter 16 electrical specifi cations (conventional products) user?s manual u14801ej3v1ud 217 (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate v dd = 2.7 to 5.5 v 78,125 bps v dd = 1.8 to 5.5 v 19,531 bps (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit t kcy3 v dd = 2.7 to 5.5 v 800 ns asck20 cycle time v dd = 1.8 to 5.5 v 3,200 ns t kh3 , t kl3 v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width v dd = 1.8 to 5.5 v 1,600 ns transfer rate v dd = 2.7 to 5.5 v 39,063 bps v dd = 1.8 to 5.5 v 9,766 bps t r , t f 1 s asck20 rise/fall time
chapter 16 electrical specifi cations (conventional products) user?s manual u14801ej3v1ud 218 ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing ti timing t tih t til ti80 1/f ti interrupt input timing intp0 to intp2 t intl t inth reset input timing reset t rsl cpt90 input timing 1/f x t xl t xh x1 input v ih3 (min.) v il3 (max.) t cpl t cph cpt90
chapter 16 electrical specifi cations (conventional products) user?s manual u14801ej3v1ud 219 serial transfer timing 3-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 remark m = 1, 2 3-wire serial i/o mode (when using ss20): uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3 t kas2 so20 ss20 output data t kds2
chapter 16 electrical specifi cations (conventional products) user?s manual u14801ej3v1ud 220 data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x ms oscillation stabilization wait time note 1 t wait release by interrupt request note 2 ms notes 1. oscillation stabilization wait time is the time in which the cpu operation is stopped to prevent unstable operation when oscillation is started. 2. selection of 2 12 /f x , 2 15 /f x , and 2 17 /f x is possible using bits 0 to 2 (o sts0 to osts2) of the oscillation stabilization time select register (osts). remark f x : system clock oscillation frequency data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operation mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode release by interrupt signal) v dd data retention mode stop mode halt mode operation mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
chapter 16 electrical specifi cations (conventional products) user?s manual u14801ej3v1ud 221 flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 1.0 5 mhz operating frequency f x v dd = 1.8 to 5.5 v 1.0 1.25 mhz write current note (v dd pin) i ddw when v pp supply voltage = v pp1 during f x = 5.0 mhz operation 18 ma write current note (v pp pin) i ppw when v pp supply voltage = v pp1 7.5 ma erase current note (v dd pin) i dde when v pp supply voltage = v pp1 during f x = 5.0 mhz operation 18 ma erase current note (v pp pin) i ppe when v pp supply voltage = v pp1 100 ma unit erase time t er 0.5 1 1 s total erase time t era 20 s write count erase/write are regarded as 1 cycle 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v note the port current (including the cu rrent that flows to the on-chip pull-up resistors) is not included.
user?s manual u14801ej3v1ud 222 chapter 17 package drawing s s h j t i g d e f c b k p l u n item b c i l m n 30-pin plastic ssop (7.62 mm (300)) a k d e f g h j p 30 16 115 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1 0.2 0.10 9.85 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 ? 0.07 1.0 0.2 3 + 5 ? 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. s30mc-65-5a4-2
user?s manual u14801ej3v1ud 223 chapter 18 recommended soldering conditions the pd789071, 789072, and 789074 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http ://www.necel.com/pkg/en/mount/index.html) table 18-1. surface mounting ty pe soldering conditions (1/2) pd789071mc- -5a4: 30-pin plastic ssop (7.62 mm (300)) pd789072mc- -5a4: 30-pin plastic ssop (7.62 mm (300)) pd789074mc- -5a4: 30-pin plastic ssop (7.62 mm (300)) pd789071mc(a)- -5a4: 30-pin plastic ssop (7.62 mm (300)) pd789072mc(a)- -5a4: 30-pin plastic ssop (7.62 mm (300)) pd789074mc(a)- -5a4: 30-pin plastic ssop (7.62 mm (300)) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: three times or less ir35-00-3 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: three times or less vp15-00-3 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature) ws60-00-1 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? pd78f9076mc-5a4: 30-pin plastic ssop (7.62 mm (300)) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: three times or less, exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours) ir35-107-3 vps package peak temperature: 215c, time: 40 seconds max. (at 200c or higher), count: three times or less, exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours) vp15-107-3 wave soldering solder bath temperatur e: 260c max. , time: 10 seconds max., count: once preheating temperature: 120c max. (pa ckage surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ws60-107-1 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering met hods together (except for partial heating).
chapter 18 recommended soldering conditions user?s manual u14801ej3v1ud 224 table 18-1. surface mounting ty pe soldering conditions (2/2) pd789071mc- -5a4-a: 30-pin plastic ssop (7.62 mm (300)) pd789072mc- -5a4-a: 30-pin plastic ssop (7.62 mm (300)) pd789074mc- -5a4-a: 30-pin plastic ssop (7.62 mm (300)) pd78f9076mc-5a4-a: 30-pin pl astic ssop (7.62 mm (300)) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) ir60-207-3 wave soldering for details, contact an nec electronics sales representative. ? partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering met hods together (except for partial heating). remark products that have the part numbers suffi xed by "-a" are lead-free products.
user's manual u14801ej3v1ud 225 appendix a development tools the following development tools are avail able for development of systems using the pd789074 subseries. figure a-1 shows the development tools. ? compatibility with pc98-nx series unless stated otherwise, products wh ich are supported by ibm pc/at tm and compatibles can also be used with the pc98-nx series. when using the pc98-nx series, t herefore, refer to the explanations for ibm pc/at and compatibles. ? windows unless stated otherwise, "windows" refe rs to the following operating systems. ? windows 3.1 ? windows 95, 98, 2000 ? windows nt tm ver. 4.0
appendix a development tools user?s manual u14801ej3v1ud 226 figure a-1. development tools software package software package assembler package c compiler package device file c library source file note 1 integrated debugger system emulator project manager (windows version only) note 2 language processing software debugging software control software host machine (pc or ews) interface adapter flash memory writing tools flash programmer in-circuit emulator power supply unit emulation board emulation probe target system conversion socket or conversion adapter flash memory writing adapter flash memory notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assemb ler package and is available only for windows.
appendix a development tools user?s manual u14801ej3v1ud 227 a.1 software package various software tools for 78k/0s development are integrated in one package. the following tools are included. ra78k0s, cc78k0s, id78k0-ns, sm 78k0s, various device files sp78k0s software package part number: s sp78k0s remark in the part number differs dependi ng on the operating system used. s sp78k0s host machine os supply medium ab17 japanese windows cd-rom bb17 pc-9800 series, ibm pc/at and compatibles english windows note also operates under the dos environment a.2 language processing software program that converts program written in mnemonic into object codes that can be executed by a microcontroller. in addition, automatic functions to generate a symbol table and optimize branch instructions are also provided. used in combination with a device file (df789076) (sold separately). the assembler package is a do s-based application but may be us ed in the windows environment by using the project manager of windows (included in the package). ra78k0s assembler package part number: s ra78k0s program that converts program written in c language into object c odes that can be executed by a microcontroller. used in combination with an assembler package (ra78k0s) and device file (df789076) (both sold separately). the c compiler package is a do s-based application but may be us ed in the windows environment by using the project manager of window s (included in the assembler package). cc78k0s c compiler package part number: s cc78k0s file containing the informat ion inherent to the device. used in combination with other tools (ra78k 0s, cc78k0s, id78k0s-ns, sm78k0s) (all sold separately). df789076 note 1 device file part number: s df789076 source file of functions constituting the obj ect library included in the c compiler package. necessary for changing the object library included in the c compiler package according to the customer's specifications. since this is a source file , its working environment does not depend on any particular operating system. cc78k0s-l note 2 c library source file part number: s cc78k0s-l notes 1. df789076 is a common file that can be used with ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s. 2. cc78k0s-l is not included in the software package (sp78k0s).
appendix a development tools user?s manual u14801ej3v1ud 228 remark in the part number differs depending on t he host machine and operating system used. s ra78k0s s cc78k0s host machine os supply media ab13 japanese windows 3.5" 2hd fd bb13 english windows ab17 japanese windows bb17 pc-9800 series, ibm pc/at and compatibles english windows cd-rom 3p17 hp9000 series 700 tm hp-ux tm (rel.10.10) 3k17 sparcstation tm sunos tm (rel.4.1.4), solaris tm (rel.2.5.1) s df789076 s cc78k0s-l host machine os supply medium ab13 japanese windows 3.5" 2hd fd bb13 pc-9800 series, ibm pc/at and compatibles english windows 3p16 hp9000 series 700 hp-ux (rel.10.10) dat 3k13 3.5" 2hd fd 3k15 sparcstation sunos (rel.4.1.4), solaris (rel.2.5.1) 1/4" cgmt a.3 control software project manager control software provided for efficient user program development in the windows environment. the project manager allows a se ries of tasks required for user program development to be performed, including starti ng the editor, building, and starting the debugger. < caution > the project manager is included in the assembler package (ra78k0s). it cannot be used in an environment other than windows.
appendix a development tools user?s manual u14801ej3v1ud 229 a.4 flash memory writing tools flashpro iii (fl-pr3, pg-fp3) flashpro iv (fl-pr4, pg-fp4) flash writer flash programmer dedicated to microcont rollers incorporating flash memory. fa-30mc flash memory writing adapter flash memory writing adapter. used in c onnection with flashpro iii or flashpro iv. 30-pin plastic ssop (mc-5a4 type) remark fl-pr3, fl-pr4, and fa-30mc are products of naito densei machida mfg. co., ltd. for further information, contact: naito d ensei machida mfg. co., ltd. (+81-45-475-4191) a.5 debugging tools (hardware) ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging hardware and software of application system using the 78k/0s series. can be used with an in tegrated debugger (id78k0s-ns). used in combination with an ac adapter, emulation probe, and interface adapter for connecting the host machine. ie-78k0s-ns-a in-circuit emulator in-circuit emulator with enhanced functions of the ie-78k0s-ns. the debug function is further enhanced by adding a coverage function and enhanc ing the tracer and timer functions. ie-70000-mc-ps-b ac adapter adapter for supplying power from a 100 to 240 vac outlet. ie-70000-98-if-c interface adapter adapter required when using a pc-9800 series (e xcept notebook type) as the host machine (c bus supported). ie-70000-cd-if-a pc card interface pc card and interface cable required when us ing a notebook type pc as the host machine (pcmica socket supported). ie-70000-pc-if-c interface adapter adapter required when using an ibm pc/at or compatible as the host machine (isa bus supported). ie-70000-pci-if-a interface adapter adapter required when using a personal comput er incorporating the pci bus as the host machine. ie-789046-ns-em1 + np-k907 emulation board emulation board for emulating the peripher al hardware inherent to the device. used in combination with an in-circuit emulator. np-30mc emulation probe probe for connecting the in-circuit emulator and target system. used in combination with nspack30bk and yspack30bk. nspack30bk yspack30bk conversion adapter conversion adapter used to connect a target system board designed to allow mounting a 30- pin plastic ssop and the np-30mc. remarks 1. np-30mc and np-k907 are products of nait o densei machida mfg. co., ltd. for further information, contact: naito densei machida mfg. co., ltd. (+81-45-475-4191) 2. nspack30bk and yspack30bk are products m ade by tokyo eletech corporation. for further information, c ontact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672)
appendix a development tools user?s manual u14801ej3v1ud 230 a.6 debugging tools (software) this debugger supports the in-cir cuit emulators ie-78k0s-ns and ie-78k0s-ns-a for the 78k/0s series. the id78k0s-n s is windows-based software. it has improved c-compatible debuggi ng functions and can display the results of tracing with the source program using an integrating window f unction that associates the source program, disassemble display, and memory display with the trace result. used in combination with a device file (df789076) (sold separately). id78k0s-ns integrated debugger part number: s id78k0s-ns this is a system simulator for the 78k/0s series. the sm78k0s is windows-based software. it can be used to debug the target system at c source level of assembler level while simulating the operation of the target system on the host machine. using sm78k0s, the logic and performance of the application can be verified independently of hardware development. therefore, the development efficiency can be enhanced and the software quality can be improved. used in combination with a device file (df789076) (sold separately). sm78k0s system simulator part number: s sm78k0s file containing the informat ion inherent to the device. used in combination with other tools (ra78k 0s, cc78k0s, id78k0s-ns, sm78k0s) (all sold separately). df789076 note device file part number: s df789076 note df789076 is a common file that can be used with ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s. remark in the part number differs depending on the oper ating system used and the supply medium. s id78k0s-ns s sm78k0s host machine os supply medium ab13 japanese windows 3.5" 2hd fd bb13 english windows ab17 japanese windows bb17 pc-9800 series, ibm pc/at and compatibles english windows cd-rom
user?s manual u14801ej3v1ud 231 appendix b notes on target system design the following show the conditions w hen connecting the emulation probe to the conversion adapter. follow the configuration below and consider t he shape of parts to be mounted on the target system when designing a system. figure b-1. distance between in-circu it emulator and conversion adapter 150 mm emulation board ie-789046-ns-em1 tgcn1 emulation probe np-30mc conversion adapter: yspack30bk, nspack30bk board on end of np-30mc in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a target system remarks 1. np-30mc is a product of naito densei machida mfg. co., ltd. 2. yspack30bk and nspack30bk are products of tokyo eletech corporation.
appendix b notes on target system design user?s manual u14801ej3v1ud 232 figure b-2. connection condition of target system 31 mm 37 mm emulation probe np-30mc 13 mm emulation board ie-789046-ns-em1 15 mm 20 mm 5 mm board on end of np-30mc conversion adapter yspack30bk, nspack30bk guide pin yqguide target system remarks 1. np-30mc is a product of naito densei machida mfg. co., ltd. 2. yspack30bk, nspack30bk, and yqguide are products of tokyo eletech corporation.
user?s manual u14801ej3v1ud 233 appendix c register index c.1 register name index (alphabetic order) 16-bit capture regi ster 90 (tcp90) ............................................................................................. ............................84 16-bit compare regi ster 90 (cr90) .............................................................................................. ...........................84 16-bit timer count er 90 (t m90) ................................................................................................. ..............................84 16-bit timer mode contro l register 90 (tmc 90) .................................................................................. .....................85 8-bit compare regi ster 80 (cr80) ............................................................................................... ............................98 8-bit timer count er 80 (t m80) .................................................................................................. ...............................98 8-bit timer mode contro l register 80 (tmc 80) ................................................................................... ......................99 [a] asynchronous serial interfac e mode register 20 (asi m20)........................................................................ ...........120 asynchronous serial interface status register 20 (asi s20)...................................................................... .............122 [b] baud rate generator contro l register 20 (brg c20) ............................................................................... ...............123 buzzer output control register 90 (bzc 90) ...................................................................................... .......................87 [e] external interrupt mode register 0 (intm0) ..................................................................................... .....................156 [i] interrupt mask flag regist er 0, 1 (mk 0, mk1) ................................................................................... .....................155 interrupt request flag regi ster 0, 1 (if0, if1)................................................................................ .........................154 [o] oscillation stabilization time selection regi ster (osts)....................................................................... ..................166 [p] port 0 (p0) ................................................................................................................... .........................................64 port 1 (p1) ................................................................................................................... .........................................65 port 2 (p2) ................................................................................................................... .........................................66 port 3 (p3) ................................................................................................................... .........................................70 port mode regist er 0 (p m0) ..................................................................................................... ...............................71 port mode regist er 1 (p m1) ..................................................................................................... ...............................71 port mode regist er 2 (p m2) ..................................................................................................... ...............................71 port mode regist er 3 (p m3) ..................................................................................................... ...............................71 processor clock cont rol regist er (pcc)......................................................................................... ..........................76 pull-up resistor option register 0 (pu0)....................................................................................... ............................72 pull-up resistor option register b2 (pub2) ..................................................................................... .........................73 [r] receive buffer regi ster 20 (rxb20)............................................................................................. .........................118
appendix c register index user?s manual u14801ej3v1ud 234 [s] serial operation mode r egister 20 (csim 20) ..................................................................................... ...................119 [t] transmission shift r egister 20 (txs20) ......................................................................................... .......................118 [w] watchdog timer clock select ion register (wdcs) ................................................................................. ................111 watchdog timer mode r egister (wdtm) ............................................................................................ ...................112
appendix c register index user?s manual u14801ej3v1ud 235 c.2 register symbol index (alphabetic order) [a] asim20: asynchronous serial interface mode register 20 ......................................................................... ......120 asis20 : asynchronous serial in terface status register 20...................................................................... .........122 [b] brgc20: baud rate generator control r egister 20 ................................................................................ ............123 bzc90: buzzer output c ontrol regi ster 90 ....................................................................................... .................87 [c] cr80: 8-bit compar e regist er 80 ................................................................................................ ....................98 cr90: 16-bit compar e regist er 90 ............................................................................................... ...................84 csim20: serial operati on mode regi ster 20 ...................................................................................... ...............119 [i] if0: interrupt reques t flag regi ster 0 ......................................................................................... ................154 if1: interrupt reques t flag regi ster 1 ......................................................................................... ................154 intm0: external interr upt mode regi ster 0...................................................................................... ...............156 [m] mk0: interrupt mask flag regist er 0 ............................................................................................ ................155 mk1: interrupt mask flag regist er 1 ............................................................................................ ................155 [o] osts: oscillation stabilization time selecti on regi ster ........................................................................ ..........166 [p] p0: port 0 .................................................................................................................. .............................64 p1: port 1 ..................................................................................................................... .............................65 p2: port 2 ..................................................................................................................... .............................66 p3: port 3 ..................................................................................................................... .............................70 pcc: processor clo ck control regist er .......................................................................................... ................76 pm0: port mode register 0 ...................................................................................................... .....................71 pm1: port mode register 1 ...................................................................................................... .....................71 pm2: port mode register 2 ...................................................................................................... .....................71 pm3: port mode register 3 ...................................................................................................... .....................71 pu0: pull-up resistor option regi ster 0 ........................................................................................ .................72 pub2: pull-up resistor option regi ster b2 ...................................................................................... .................73 [r] rxb20: receive bu ffer regist er 20.............................................................................................. ...................118 [t] tcp90: 16-bit capt ure regist er 90 .............................................................................................. ......................84 tm80: 8-bit time r counter 80 ................................................................................................... .......................98 tm90: 16-bit time r counter 90 .................................................................................................. ......................84 tmc80: 8-bit timer mode control regi ster 80 .................................................................................... ................99
appendix c register index user's manual u14801ej3v1ud 236 tmc90: 16-bit timer mode control regi ster 90 ................................................................................... ...............85 txs20: transmission sh ift regist er 20 .......................................................................................... .................118 [w] wdcs: watchdog timer clo ck selection regist er.................................................................................. ..........111 wdtm: watchdog time r mode r egister............................................................................................. .............112
user's manual u14801ej3v1ud 237 appendix d revision history the following shows the revision history. ?chapter? re fers to the chapters in the respective edition. (1/2) edition description chapter 2nd edition change of pd789071, 789072, 789074, and 78f9076 from under development to development complete. throughout modification of description of vpp pin connection chapter 2 pin function modification of caution on rewriting cr90 in 6.4.1 operation as timer interrupt chapter 6 16-bit timer 90 addition of description on reading receive data of uart chapter 9 serial interface 20 addition of note on unused pins in table 13-2 communication mode addition of note and remark to figures 13-2 flashpro iii connection example in 3-wire serial i/o mode , 13-3 flashpro iii connection example in uart mode , and 13-4 flashpro iii connection example in pseudo 3-wire mode modification of value of uart in table 13-4 setting example with pg- fp3 addition of 13.1.5 on-board pin connections chapter 13 pd78f9076 addition of electric al specifications chapter 15 electrical specifications addition of package drawing chapter 16 package drawing addition of recommended soldering conditions chapter 17 recommended soldering conditions overall modification of de scription on development tools deletion of embedded software appendix a development tools 3rd edition ? addition of pd789071(a), 789072(a), and 789074(a) ? addition of description of expanded-specificat ion products throughout ? addition of 1.1 expanded-specification products and conventional products ? addition of 1.5 quality grades ? addition of 1.10 differences between standard quality grade products and (a) products chapter 1 general ? modification of description of 6.4.1 operation as timer interrupt ? modification of description of 6.4.2 operation as timer output ? addition of 6.5 notes on using 16-bit timer 90 ? modification of figure 6-6. timing of timer interrupt operation ? modification of figure 6-8. timer output timing chapter 6 16-bit timer 90 ? addition of 7.5 (3) timer operation after compare register is rewritten during pwm output ? addition of 7.5 (4) cautions when stop mode is set ? addition of 7.5 (5) start timing of external event counter chapter 7 8-bit timer/event counter 80 total revision of description of flash memory programming chapter 13 pd78f9076
appendix d revision history user?s manual u14801ej3v1ud 238 (2/2) edition description chapter 3rd edition addition of chapter chapter 15 electrical specifications (expanded-specification products) modification of table of recommended oscillator constant chapter 16 electrical specifications (conventional products) change of recommended soldering conditions of pd78f9076 chapter 18 recommended soldering conditions modification of description of a.5 debugging tools (hardware) appendix a development tools addition of chapter appendix b notes on target system design modification of 1.4 ordering information modification of 1.5 quality grades chapter 1 general 3rd edition (modification version) addition of table 18-1. surface mounting type soldering conditions (2/2) chapter 18 recommended soldering conditions

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